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Low-power Charge-pump Based Switched-capacitor CircuitsNilchi, Alireza 09 August 2013 (has links)
In this thesis, low-power charge-pump (CP) based switched-capacitor (SC) circuits are proposed. The approach is validated in SC integrators and gain stages, and is shown to achieve power savings compared to conventional SC circuits. For the same thermal noise and settling performance, a CP based integrator with N sampling capacitors ideally consumes N^2 times lower OTA power compared to a conventional integrator. Practical effects such as the OTA
partial slew-rate limitation and the CP parasitics reduce the power savings. In the case of a SC gain stage, reduction in power savings also occurs due to the load capacitance from the next stage. A prototype delta-sigma modulator employing a CP integrator at the front-end is
fabricated. Experimental results demonstrate that the CP based ADC achieves the same performance as a conventional ADC while consuming three times lower OTA power in the front-end integrator. The CP ADC achieves 87.8 dB SNDR 89.2 dB SNR and 90 dB DR over a 10 kHz bandwidth while consuming 148 uW from a 1.2 V power supply. The conventional ADC
has similar performance but dissipates 241 uW. The CP ADC figure-of-merit (FOM) is 0.369
pJ/conv-step, which is almost 40% lower than that of the conventional ADC.
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Continuous time input pipeline ADCs /Gubbins, David Patrick. January 1900 (has links)
Thesis (Ph. D.)--Oregon State University, 2009. / Printout. Includes bibliographical references (leaves 76-77). Also available on the World Wide Web.
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OP-AMP free SC biquad LPF and delta-sigma ADC /Yoo, Kiseok. January 1900 (has links)
Thesis (M.S.)--Oregon State University, 2004. / Printout. Includes bibliographical references (leaves 39-40). Also available on the World Wide Web.
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Design of CMOS wide-band switched-capacitor bandpass filters /Ng, Wai Hon. January 2002 (has links)
Thesis (M. Phil.)--Hong Kong University of Science and Technology, 2002. / Includes bibliographical references. Also available in electronic version. Access restricted to campus users.
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Area efficient charge pumps and post low dropout regulators /Ying, Tianrui. January 2002 (has links)
Thesis (M. Phil.)--Hong Kong University of Science and Technology, 2002. / Includes bibliographical references. Also available in electronic version. Access restricted to campus users.
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Entwurf von Schalter Kondensator Filtern mit Spannungsumkehrschaltern...Pandel, Jürgen. January 1983 (has links)
Thesis (Ph. D.)--Ruhr Universität Bochum, 1983. / Vita.
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Switched-capacitor network synthesis using leapfrog methodLeonardi, Suryanto Felix, 1958-, Leonardi, Suryanto Felix, 1958- January 1989 (has links)
No description available.
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A data acquisition system with switched capacitor sample-and-holdHarbour, Kenton Dean January 2011 (has links)
Typescript (photocopy). / Digitized by Kansas State University Libraries / Department: Electrical Engineering.
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Low-voltage switched-capacitor circuitsBidari, Emad 25 November 1998 (has links)
In recent years, the rapidly growth of CMOS technology has evolved towards submicron and deep-submicron features. Due to smaller device sizes, and significant demand for low-power designs, the maximum allowable power supply voltage is restricted. So far, two solutions; clock boosting and switched opamp schemes have been proposed. The material presented in this thesis shows the drawback of these schemes while presenting three new methods for realizing low-voltage switched-capacitor integrators which are the key stages of ����� modulators and SC filters.
Using these integrators, several circuit realizations of SC filters and second order ����� modulators will be shown. / Graduation date: 1999
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MOSFET-only predictive track and hold circuitQiu, Xiangping 19 March 1997 (has links)
High-accuracy and high-speed CMOS track-and-hold (T/H) or sample-and-hold (S/H) circuits are an important part of the analog-to-digital interface. The switched-capacitor (SC) circuits usually contain one or more op-amps whose dc offset, finite gain, finite bandwidth have a big impact on the accuracy of the track-and-hold circuit. Basic correlated double sampling (CDS) scheme can reduce such effects, but the compensation that it provides may not be good enough for high-accuracy application. Also, the high-quality analog poly-poly capacitors used in most SC circuits are not available in a basic digital CMOS process. The MOSFET-only predictive track-and-hold circuit, discussed in this thesis, replaces the poly-poly capacitors with easily-available low-cost area-saving MOSFET capacitors biased in accumulation region. It also uses the predictive correlated double sampling (CDS) scheme, in which the op-amp
predicts its output for the next clock period during the present clock period, so that the adjacent two output samples are nearly the same. The predictive operation results in more correlation between the unwanted signal and the signal that is subtracted during the double sampling, and hence can achieve offset and gain compensation over wider frequency range. Hence, this circuit is suitable for high-accuracy applications, while using only a basic digital process. / Graduation date: 1997
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