University of Macau / Faculty of Science and Technology / Department of Electrical and Electronics Engineering

Thesis (Ph. D.)--Ohio University, March, 1999. / Title from PDF t.p.

Thesis (M. App. Sc.)--Carleton University, 2003. / Includes bibliographical references (p. 140-143). Also available in electronic format on the Internet.

Thesis (M.S.)--Missouri University of Science and Technology, 2010. / Vita. The entire thesis text is included in file. Title from title screen of thesis/dissertation PDF file (viewed July 26, 2010) Includes bibliographical references (p. 96-102).

Thesis (M.S.)--Montana State University--Bozeman, 2004. / Typescript. Chairperson, Graduate Committee: Todd J. Kaiser. Includes bibliographical references (leaves 169-171).

Switched-capacitor (SC) DC-DC converters provide a viable solution for on-chip DC-DC conversion as all the components required are available in most processes. However, power efficiency, power density characteristics of SC converters are adversely affected by the integration, and characteristics such as response time and noise can be further improved with an on-chip converter. An analysis on speed, power efficiency, and noise performance of SC converters is presented and verified using simulations. Based on the analysis two techniques, converter-gating and adaptive gain control, are developed. Converter-gating uses a combination of smaller stages and reconfiguration during transient load steps to improve the power efficiency and transient response speed. The stages of the converter are also distributed across the die to reduce the voltage drop and noise on power supply. Adaptive gain control improves transient response through manipulation of the gain of the integrator in the control loop. This technique focuses on improving the response time during converter reconfiguration and offers a general solution to transient response improvement instead of focusing on the worst case scenario which is usually the largest transient load step. The techniques developed are then implemented in ST 28nm FDSOI process and test methodologies are discussed.

Two new classes of soft switching pulse-width-modulated (PWM) converters, named zero-voltage-switched (ZVS) PWM converters and zero-voltage-transition (ZVT) PWM converters, are proposed. The proposed ZVS-PWM converters combine the merits of conventional PWM and ZVS-QRC techniques. They are capable of regulating the output for a wide load and input voltage range while maintaining constant-frequency operation. By employing a saturable inductor, the load range under which ZVS is maintained can be significantly extended without increasing the voltage stress of the power switch. The parasitic oscillations between the diode junction capacitance and the resonant inductor are also significantly reduced. In the new class of ZVT-PWM converters, both the power switch and the rectifier diode are operated with zero-voltage switching, and are subjected to low voltage and current stresses associated with those in their PWM counterparts. Thus switching losses are significantly reduced at a slight increase in conduction losses. In addition, the circuit optimization is simplified because of constant-frequency operation. The operation principles of the proposed converters are described by using several examples. Several breadboarded converters are implemented to verify the theoretical analysis and to demonstrate the feasibility of the proposed technologies. / Master of Science

Thesis (MScEng (Electrical and Electronic Engineering))--University of Stellenbosch, 2005. / A switching state substitution must be developed that will make use of both single-phase redundancies and three-phase redundancies in the flying-capacitor topology. Losses should be taken into consideration and the algorithm must be designed for implementation on the existing PEC33 system, with on-board DSP (TMS320VC33) and FPGA (EP1K50QC208). The specific power-electronics application is a medium-voltage active filter. Existing capacitor voltage stabilisation schemes are investigated and a capacitor-voltage based algorithm is developed that is investigated in parallel with the Donzel and Bornard algorithm. Detailed simulation models are built for the evaluation of both existing and the proposed algorithm. Three-phase control is also evaluated. Timing analysis of the proposed algorithm shows that a DSP-only implementation of the proposed capacitor-based solution is not feasible. Detail design of the digital controller hereof is implemented in VHDL. Finally, a four-cell controller is fitted into the FPGA. A scalable hardware sorting architecture is utilised.

The most accurate method for performing analog signal processing in MOS (metal-oxide-semiconductor) integrated circuits is through the use of switched-capacitor circuits. A switched-capacitor circuit operates as a discrete-time signal processor. These circuits have been used in a variety of applications, such as filters, gain stages, voltage-controlled oscillators, and modulators. A switched-capacitor circuit contains operational amplifiers (opamps), capacitators, switches, and a clock generator. Capacitors are used to define the state variables of a system. They store charges for a defined time interval, and determine the state variables as voltage differences. Switches are used to direct the flow of charges and to enable the charging and discharging of capacitors. Nonoverlapping clock signals control the switches and allow charge transfer between the capacitors. Opamps are used in order to perform high-accuracy charge transfer from one capacitor to another. The goal of this research is to design and explore future low-voltage switched-capacitor circuits, which are crucial for portable devices. Low-voltage operation is needed for two reasons: making reliable and accurate systems compatible with the submicron CMOS technology and reducing power consumption of the digital circuits. To this end, three different switched-capacitor integrators are proposed, which function with very low supply voltages. One of these configurations is used to design a lowpass ����� modulator for digital-audio applications. This modulator is fabricated and tested demonstrating 80 dB dynamic range with a 1-V supply voltage. The second part of this research is to show that these low-voltage circuits are suitable for modern wireless communication applications, where the clock and signal frequencies are very high. This part of the research has focused on bandpass analog-to-digital converters. Bandpass analog-to-digital converters are among the key components in wireless communication systems. They are used to digitize the received analog signal at an intermediate center frequency. Such converters are used for digital FM or AM radio applications and for portable communication devices, such as cellular phones. The main block, in these converters, is the resonator, which is tuned to a particular center frequency. A resonator must be designed such that it has a sharp peak at a specific center frequency. However, because of circuit imperfections, the resonant peak gain and/or the center frequency are degraded in existing architectures. Two novel switched-capacitor resonators were invented during the second part of this research. These resonators demonstrate superior performance as compared to previous architectures. A fourth-order low-voltage bandpass ����� modulator, using one of these resonators, has been designed. / Graduation date: 2002

University of Macau / Faculty of Science and Technology / Department of Electrical and Electronics Engineering