Pipelined analog to digital converters (ADCs) are very important building blocks in many electronic systems such as high quality video systems, high performance digital communication systems and high speed data acquisition systems. The rapid development of these applications is driving the design of pipeline ADCs towards higher speed, higher dynamic range, lower power consumption and lower power supply voltage with the CMOS technology scaling. This trend poses great challenges to conventional pipelined ADC designs which rely on high-gain operational amplifiers (opamps) and well matched capacitors to achieve high accuracy. In this thesis, two novel accuracy improvement techniques to overcome the accuracy limit set by analog building blocks (opamps and capacitors) in the context of low-voltage and high-speed pipelined ADC design are presented. One is the time-shifted correlated double sampling (CDS) technique which addresses the finite opamp gain effect and the other is the radix-based background digital calibration technique which can take care of both finite opamp gain and capacitor mismatch. These methods are simple, easy to implement and power efficient. The effectiveness of the proposed techniques is demonstrated in simulation as well as in experiment. Two prototype ADCs have been designed and fabricated in 0.18μm CMOS technology as the experimental verification of the proposed techniques. The first ADC is a 1.8V 10-bit pipeline ADC which incorporated the time-shifted CDS technique to boost the effective gain of the amplifiers. Much better gain-bandwidth tradeoff in amplifier design is achieved with this gain boosting. Measurement results show total power consumption of 67mW at 1.8V when operating at 100MSPS. The SNR, SNDR and SFDR are 55dB, 54dB and 65dB respectively given a 1MHz input signal. The second one is a 0.9V 12-bit two-stage cyclic ADC which employed a novel correlation-based background calibration to enhance the linearity. The linearity limit set by the capacitor mismatches, finite opamp gain effects is exceeded. After calibration, the SFDR is improved by about 33dB and exceeds 80dB. The power consumption is 12mW from 0.9V supply when operating at 2MSPS. / Graduation date: 2004

Switched-capacitor (SC) circuits are commonly used for analog signal processing because they can be used to realize precision filters and data converters on an integrated circuit (IC). However, for high speed applications SC circuit operating speeds are limited by the internally-compensated opamps found in SC integrators, a common building block of these circuits. This thesis studies gain stages that eliminate the internal compensation, thus allowing the SC circuits to operate at significantly higher operating speeds. An inverter-based SC integrator is presented. The proposed SC integrator is built with a pseudo-differential structure to improve its rejection of common-mode noise, such as charge injection and clock feedthrough. The proposed integrator also incorporates correlated double sampling (CDS) to boost its effective DC gain. Clock-boosting and switch bootstrapping techniques are not used in the proposed circuit, even though it uses a low supply voltage. To verify the speed advantage of the proposed circuit, a high speed delta sigma (Δ∑) modulator was designed in a 1.8V, 0.18μm CMOS technology. The designed Δ∑ modulator operates at a clock frequency of 500MHz. Circuit implementation and layout floorplan are described. The design is based on MATLAB and SpectreS simulations. / Graduation date: 2002

Recently, switched capacitor DC/DC converters are extensively used in portable electronic devices because they feature many advantages, such as high efficiency, small package, low quiescent current, minimal external components and low cost. In this thesis, two step-down switched capacitor DC/DC converters are designed. One has the fixed output options 1.5V, 1.8V and 2.0V. The other one has the output 1.2V. These two converters are implemented in 0.5��m CMOS process through National Semiconductor Corporation. The design is verified by the circuit-level simulations, and design issues are discussed. / Graduation date: 2004

This thesis describes compensation techniques for cascaded delta-sigma A/D converters (ADCs) and high-performance switched-capacitor (SC) circuits. Various correlated-double-sampling (CDS) techniques are presented to reduce the effects of the nonidealities, such as clock feedthrough, charge injection, opamp input-referred noise and offset, and finite opamp gain, in SC circuits. A CDS technique for the compensation of opamp input-referred offset and clock-feedthrough effect is examined and improved to achieve continuous operation. Experimental results show that after the compensation, the SC integrator's output signal swing is greatly increased. The effects of the analog circuitry nonidealities in delta-sigma ADCs are also analyzed. The analysis shows that the nonidealities in cascaded delta-sigma ADCs cause noise leakage, which limits the overall performance of the cascaded modulators. In order to reduce the noise leakage, a novel adaptive compensation technique is proposed. To verify the effectiveness of the proposed compensation techniques, a prototype 2-0 cascaded modulator was designed. Its first stage, a second-order delta-sigma modulator with test signal input circuit, was designed and fabricated in 1.2 ��m CMOS technology. The measurement results show that the noise leakage is reduced effectively by the compensation, and the performance of the cascaded delta-sigma modulator is greatly improved. / Graduation date: 1999

Thesis (M.S.)--Oregon State University, 2007. / Printout. Includes bibliographical references (leaves 82-86). Also available on the World Wide Web.

This thesis investigates the various techniques to achieve large time constants and the ultimate limitations therein. A novel circuit technique for the realization of large time constants for high pass corners in switched-capacitor filters is also proposed and compared with existing techniques. The switched-capacitor technique is insensitive to parasitic capacitances and is area efficient and it requires only two clock phases. The circuit is used to build a typical switched-capacitor front end with a gain of 10. The low pass corner is fixed at 200 Hz. The high pass corner is varied from 0.159Hz to 4 Hz and various performance parameters, such as power consumption, silicon area etc., are compared with conventional techniques and the advantages and disadvantages of each technique are demonstrated. The front-ends are fully differential and are chopper stabilized to protect against DC offsets and 1/f noise. The front-end is implemented in AMI0.6um technology with a supply voltage of 1.6V and all transistors operate in weak inversion with currents in the range of tens of nano-amperes.

In computer science, real-time research is an interesting topic. Nowadays real-time applications are close to us in our daily life. Skype, MSN, satellite communication, automation car and Ethernet are all things related to the real-time field. Many of our computer systems are also real-time, such as RT-Linux, Windows CE. In other words, we live in a “real-time” world. However, not everyone knows much about its existence. Hence, we chose this thesis in order to take a knowledge journey in the real-time field. For an average reader, we hope to provide some basic knowledge about real-time. For a computer science student, we will try to provide a discussion on switched multi-hop network with offsets, and the influence of offsets on real-time network performance. We try to prove that offsets provide networks of high predictability and utilization because offsets adjust packet‟s sending time. A packet‟s sending time is the time when a sender/router starts to transmit a date packet. Packets are sent one after the other. Therefore, we need to lower the time interval between one packet and another. Hence, in our network model, network performance is more predictable and effective. There might be some things left to discuss in future, so we would like to receive any advice and also suggestions for future discussions.

Ethernet technology is being accepted by industrial community due to its open standardization and low cost. To meet the requirements of industrial applications, a switched Ethernet network with hard real time guarantees using relative deadlines is presented as a first step to verify the functionality. The goal of the project was primarily to implement a real-time switched Ethernet with EDF (Earliest Deadline First) scheduling algorithm. In this project, the function simulations of real-time switched Ethernet with distributed control software have been implemented, by using a standard switch with priority-queues and the distributed software, as well as EDF-scheduled TDMA (Time Division Medium Access). The network topology is the star type. There is no extra hardware added into the switch and the nodes. All functions are implemented by software and the setting in the switch. The project focuses on hard real-time service guarantees but soft real-time traffic and non real-time traffic, as well as real time administration are also taken into the consideration. Our simulations show that 100 percent of the network usage could be scheduled and the result of deterministic real-time properties of the system are achieved as expected.

The aim of this Master’s thesis is to develop a solution for combining speed and performance of switched Ethernet with the real time capability and determinism of sophisticated in- vehicle networks. After thorough research in vehicle network standards, their demands and features, the Flexible Time Division Multiple Access (FTDMA) protocol of FlexRay was chosen to be applied on a switched Ethernet architecture since it can accommodate both hard real time tasks and soft real time tasks. To provide hard real time capability, what this paper focuses on, a media access method was developed by creating static TDMA schedules for each node’s sending and receiving port according to a certain traffic assumption. To validate the developed media access algorithm several examples with different traffic assumptions and architectures were generated and investigated based on their sending and receiving utilization. A second method for validating and thus proving the functionality of the algorithm was by simulation. Therefore the Matlab Simulink media library extension TRUE TIME was used to simulate a simple example with 100% sending and receiving utilization for each node.

This thesis introduces the notion of using stability analysis in terms of two measures for impulsive switched systems. Impulsive switched systems are defined in the context of hybrid system theory and the motivation for the study of these systems is presented. The motivation for studying stability in two measures is also given, along with the definitions of stability, uniform stability, and uniform asymptotic stability in one and two measures. The results presented are a sets of sufficient stability criteria for linear and nonlinear systems. For autonomous linear systems, there are criteria for stability and asymptotic stability using a particular family of choices for the two measures. There is an additional stronger set of criteria for asymptotic stability using one measure, for comparison. There is also a proposed method for finding the asymptotic stability of a non-autonomous system in one measure. The method for extending these criteria to linearized systems is also presented, along with stability criteria for such systems. The criteria for nonlinear systems cover stability, uniform stability, and uniform asymptotic stability, considering state-based and time-based switching rules in different ways. The sufficient stability criteria that were found were used to solve four instructive examples. These examples show how the criteria are applied, how they compare, and what the shortcomings are in certain situations. It was found that the method of using two measures produced stricter stability requirements than a similar method for one measure. It was still found to be a useful result that could be applied to the stability analysis of an actual impulsive switched system.