Thesis (MAppSc (Comp & InfoSc))--University of South Australia, 1997

Thesis (M.S.)--Rochester Institute of Technology, 1993. / Typescript. Includes bibliographical references.

Modern electronic systems, especially sensor and imaging systems, are beginning to incorporate their own neural network subsystems. In order for these neural systems to learn in real-time they must be implemented using VLSI technology, with as much of the learning processes incorporated on-chip as is possible. The majority of current VLSI implementations literally implement a series of neural processing cells, which can be connected together in an arbitrary fashion. Many do not perform the entire neural learning process on-chip, instead relying on other external systems to carry out part of the computation requirements of the algorithm. The work presented here utilises two dimensional instruction systolic arrays in an attempt to define a general neural architecture which is closer to the biological basis of neural networks - it is the synapses themselves, rather than the neurons, that have dedicated processing units. A unified architecture is described which can be programmed at the microcode level in order to facilitate the processing of multiple neural network types. An essential part of neural network processing is the neuron activation function, which can range from a sequential algorithm to a discrete mathematical expression. The architecture presented can easily carry out the sequential functions, and introduces a fast method of mathematical approximation for the more complex functions. This can be evaluated on-chip, thus implementing the entire neural process within a single system. VHDL circuit descriptions for the chip have been generated, and the systolic processing algorithms and associated microcode instruction set for three different neural paradigms have been designed. A software simulator of the architecture has been written, giving results for several common applications in the field.

The computer performance has been improved tremendously since the development of the first allpurpose, all electronic digital computer in 1946. However, engineers, scientists and researchers keep making more efforts to further improve the computer performance to meet the demanding requirements for many applications. There are basically two ways to improve the computer performance in terms of computational speed. One way is to use faster devices (VLSI chips). Although faster and faster VLSI components have contributed a great deal on the improvement of computation speed, the breakthroughs in increasing switching speed and circuit densities of VLSI devices will be diflicult and costly in future. The other way is to use parallel processing architectures which employ multiple processors to perform a computation task. When multiple processors working together, an appropriate architecture is very important to achieve the maximum performance in a cost-effective manner. Systolic arrays are ideally qualified for computationally intensive applications with inherent massive parallelism because they capitalize on regular, modular, rhythmic, synchronous, concurrent processes that require intensive, repetitive computation. This thesis can be divided into three parts. The first part is an introductory part containing Chap. I and Chap. 2. The second part, composed of Chap. 3 and Chap. 4 concerns with the systolic design methodology. The third part deals with the several systolic array design for different applications.

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Στο πλαίσιο αυτής της εργασίας μελετήθηκαν οι διατάξεις επεξεργαστών και πιο συγκεκριμένα οι συστολικές διατάξεις επεξεργαστών. Επίσης αναπτύχθηκε CAD εργαλείο για την αυτόματη VLSI σχεδίαση συστολικών διατάξεων επεξεργαστών για αλγόριθμους επεξεργασίας σήματος. / In this book were studied the processor arrays and more concretely the systolic processor arrays. Also was developed CAD tool for the automatic VLSI designing of systolic processor arrays on signal processing algorithms.

The focus of this thesis is on the design and selection of systolic architectures for ASIC implementation of the real-time digital signal processing task of Modi- fied Covariance spectral estimation. When used with pulsed Doppler ultrasound blood flow detectors, the Modified Covariance spectral estimator offers increased sensitivity in the detection of arterial disease over conventional Fourier transform based methods. The systolic model of computation is considered because through pipelining and parallel processing high levels of concurrency can be achieved to attain the nec- essary throughput for real-time operation. Systolic arrays of simple processing units are also well suited for implementation on VLSI. The versatility of the de- sign of systolic arrays using the rigorous data dependence graph methodology is demonstrated throughout the thesis by application to all sections of the spectral estimator design at both word and bit levels. Systolic array design for the model order 4 Modified Covariance spectral estima- tor, known to offer accurate estimation of blood flow mean velocity and d1stur- bance at an acceptable computational burden, is initially discussed. A variety of problem size dependent systolic arrays for real-time implementation of the fixed model order spectral estimator are designed using data dependence graph mapping methods. Optimal designs are chosen by comparison of hardware, com- munication and control costs, as well as efficiency, timing, data flow and accuracy considerations. A cost/benefit analysis, based on results from structural simula- tion of the arrays, allows the most suitable word-lengths to be chosen. Problem size independent systolic arrays are then discussed as means of coping with the huge increases in computational burden for a Modified Covariance spec- tral estimator which is programmable up to high model orders. This type of array can be used to reduce the number of PEs and increase efficiency when compared to the problem size dependent arrays and the research culminates in the proposal of a novel spiral systolic array for Cholesky decomposition.

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International Telemetering Conference Proceedings / October 30-November 02, 1995 / Riviera Hotel, Las Vegas, Nevada / This paper describes the development of a Reed-Solomon (RS) Encoder-Decoder which implements the RS segment of the telemetry channel coding scheme recommended by the Consultative Committee on Space Data Systems (CCSDS)[1]. The Euclidean algorithm has been chosen for the decoder implementation, the hardware realization taking a systolic array approach. The fully pipelined decoder runs on a single clock and the operating speed is limited only by the Galois Field (GF) multiplier's delay. The circuit has been synthesised from VHDL descriptions and the hardware is being realised using programmable logic chips. This circuit was simulated for functional operation and found to perform correction of error patterns exactly as predicted by theory.

This thesis focuses on the Binary Integer Modulo-Division Algorithm that is essential for the permutation process in Sunar-Koc ONB Type II Multiplier and also for other general purposes. This thesis explains the new algorithm developed based on the systolic array architecture which gives a systematic approach to the iterative process for the Modulo-Division. The scheduling and projection timing functions are proposed for the processor array allocation and the matlab code has been implemented to verify the efficiency of the algorithm. The thesis also explores the possibility of word based algorithm for design optimisation. / Graduate / 0544 / 0984 / m.shubha8@gmail.com