Snehal Udar, for the Doctor of Philosophy degree in Electrical and Computer Engineering, presented on May 4, of 2011, at Southern Illinois University Carbondale. TITLE: BUILT-IN SCHEMES FOR TEST PATTERN GENERATION AND FAULT LOCATION MAJOR PROFESSOR: Dr. D. Kagaris In this dissertation, we studied the areas of test pattern generation and fault location for detecting and diagnosing the faults in today's complex chips. In the first problem, a novel reseeding based test pattern generation scheme is analyzed by proposing a hardware efficient technique that uses irreducible polynomial-primitive element pair to generate distinct subsequences of test patterns. It is shown that for the given characteristic polynomial the hardware cost remains the same irrespective of the number of seeds required to generate the test sequence of given length. This scheme is targeted at generating pseudo-random test patterns that detect easy-to-detect faults. A counter based reseeding scheme is further analyzed that embeds a given set of fully specified test patterns in minimum number of clock cycles. Second problem investigates the effectiveness of inserting observation points on the circuit lines that along with primary output lines distinguish a given set of faults. Three hardware based approaches are proposed that aim at inserting minimum observation points, and are compared with each other for different diagnostic resolutions.

When we survey hardware design groups, we can find that it is now dedicated to verification between 60 to 80 percent. According to the instruction set architecture information should be a feasible and reasonable way for generating the test pattern to verify the function of a microprocessor. In this these, we¡¦ll present an instruction test pattern (for microprocessors) generation method based on the instruction set architecture. It can help the users to generate the instruction test pattern efficiently. The generation flow in this thesis contains three major flows: individual instruction, instruction pair, and manual generation. They are used for different verification cases. The ¡§individual instruction¡¨ could be used for verifying the functions of each implemented instructions. The ¡§instruction pair¡¨ could be used for verifying the interaction of instruction execution in a pipeline for a HDL implementation of a microprocessor. The ¡§manual generation¡¨ could be used to verify some corner cases (behaviors) of the microprocessor. As the quality of our test pattern, we generate some patterns for 32-bits instruction (ARM instruction sets and SPARC instruction sets) and use them to verify a synthesizable RTL core. With some handwriting test pattern (34.7%), our automatic generation method can approach 100% HDL code coverage of the microprocessor design. We use the HDL code coverage as the reference of test pattern quality. Because our generation method is based on the instruction field, we can describe most instruction set for the generator. Hence, our generation method can retarget to most instruction set architecture without modifying the generator. Besides the RISC instructions, even the CISC instructions could be generated.

Thesis(M.S.)--Auburn University, 2006. / Abstract. Vita. Includes bibliographic references (p.74-78).

No description available.

This thesis presents four different techniques for improving the average-case performance of deterministic sequential circuit Automatic Test Patterns Generators (ATPG). Three techniques make use of information gathered during test generation to help identify more unjustifiable states with higher percentage of "don't care" value. An approach for reducing the search space of the ATPG was introduced. The technique can significantly reduce the size of the search space but cannot ensure the completeness of the search. Results on ISCAS–85 benchmark circuits show that all of the proposed techniques allow for better fault detection in shorter amounts of time. These techniques, when used together, produced test vectors with high fault coverages. Also investigated in this thesis is the Decision Inversion Problem which threatens the completeness of ATPG tools such as HITEC or ATOMS. We propose a technique which can eliminate this problem by forcing the ATPG to consider search space with certain flip-flops untouched. Results show that our technique eliminated the decision inversion problem, ensuring the soundness of the search algorithm under the 9-valued logic model. / Master of Science

Dėl didėjančio integrinių schemų sudėtingumo ir darbinių dažnių vėlinimo gedimų nustatymas tampa svarbia schemų kūrimo dalimi. Programiniai schemų prototipai leidžia atlikti schemų testavimą ankstyvojoje stadijoje. Šiame darbe yra pateikiama vėlinimo gedimų nustatymo metodų analizė ir jų palyginimas. Tyrimo objektu pasirinktas perėjimo gedimų modelis. Dokumente aprašomas AntiRandom metodo pritaikymo galimybės funkcinių testų generavimui. Taip pat yra trumpai apžvelgiami egzistuojantys sprendimai rinkoje. Projektavimo skyriuje yra aprašoma suprojektuota ir realizuota sistema, kuri susideda iš dviejų posistemių: funkcinių testų generatoriaus bei rezultatų kaupimo ir analizės posistemės. Funkcinių testų generatoriuje realizuoti du atsitiktinio ir AntiRandom metodai. Paskutinėje dokumento dalyje yra pateiktas atliktas eksperimentinis tyrimas su realizuota sistema. Taip pat yra pateikiami eksperimentinio tyrimo metu pasiekti rezultatai bei padarytos viso darbo išvados. / The increasing complexity of integrated circuits and operating frequency led delay fault identification to become an important part of the schemes development. Software prototypes allow to start testing phase at an early stage. This work covers the delay fault detection method analysis and comparison. For the study is selected transition fault identification. The paper describes the AntiRandom method and customization possibilities for the functional test generation. There is also a brief overview of an existing solutions on the market. The design section describes the designed and implemented system which consists of two subsystems: functional tests generator and results storage and analysis subsystem. Functional test generator has two random methods and customized AntiRandom method. The last part of the document covers an experimental study for the created system. It consists of results of the experiments and conclusions of the whole work.

With rapid advancement in science and technology and decreasing feature size of transistors, the complexity of VLSI designs is constantly increasing. With increasing density and complexity of the designs, the probability of occurrence of defects also increases. Therefore testing of designs becomes essential in order to guarantee fault-free operation of devices. Testing of VLSI designs involves generation of test patterns, test pattern application and identification of defects in design. In case of scan based designs, the test set size directly impacts the test application time which is determined by the number of memory elements in the design and the test storage requirements. There are various methods in literature which are used to address the issue of large test set size classified as static or dynamic compaction methods depending on whether the test compaction algorithm is performed as a post-processing step after test generation or is integrated within the test generation. In general, there is a trade-off between the test compaction achievable and the run-time. Methods which are computationally intensive might provide better compaction, however, might have longer run times owing to the complexity of the algorithm. In the first part of the thesis we address the problem of large test set size in partially scanned designs by proposing an incremental dynamic compaction method. Typically, the fault coverage curve of designs ramp up very quickly in the beginning and later slows down and ultimately the curve flattens towards the tail of the curve. In the initial phase of test generation a greedy compaction method is used because initially there are easy-to-detect faults and the scope for compaction is better. However, in the later portion of the curve, there are hard-to-detect faults which affect compaction and we propose to use a dynamic compaction approach. We propose a novel mechanism to identify redundant faults during dynamic compaction to avoid targeting them later. The effectiveness of method is demonstrated on industrial designs and test size reduction of 30% is achieved. As the device complexity is increasing, delay defects are also increasing. Speed path debug is necessary in order to meet performance requirements. Speed paths are the frequency limiting paths in a design identified during debug. Speed paths can be tested using functional patterns, transition n-detect patterns or path delay patterns. However, usage of functional patterns for speed path debug is expensive because generation of functional patterns is expensive and the application cost is also high because the number of patterns is large and requires functional testers. In the second part of the dissertation we propose a simple path sensitization approach that can be used to generate pseudo-robust tests, which are near robust tests and can be used for designs that have multiple clock domains. The fault coverage for path delay fault APTG can be further improved by dividing the paths that are not testable under pseudo robust conditions, into shorter sub-paths. The effectiveness of the method is demonstrated on industrial designs.

Capacitive crosstalk between adjacent signal wires in integrated circuits may lead to noise or a speedup or slowdown in signal transitions. These in turn may lead to circuit failure or reduced operating speed. This thesis focuses on generating test patterns to induce crosstalk-induced signal delays, in order to determine whether the circuit can still meet its timing specification. A timing-driven test generator is developed to sensitize multiple aligned aggressors coupled to a delay-sensitive victim path to detect the combination of a delay spot defect and crosstalk-induced slowdown. The framework uses parasitic capacitance information, timing windows and crosstalk-induced delay estimates to screen out unaligned or ineffective aggressors coupled to a victim path, speeding up crosstalk pattern generation. In order to induce maximum crosstalk slowdown along a path, aggressors are prioritized based on their potential delay increase and timing alignment. The test generation engine introduces the concept of alignment-driven path sensitization to generate paths from inputs to coupled aggressor nets that meet timing alignment and direction requirements. By using path delay information obtained from circuit preprocessing, preferred paths can be chosen during aggressor path propagation processes. As the test generator sensitizes aggressors in the presence of victim path necessary assignments, the search space is effectively reduced for aggressor path generation. This helps in reducing the test generation time for aligned aggressors. In addition, two new crosstalk-driven dynamic test compaction algorithms are developed to control the increase in test pattern count. The proposed test generation algorithm is applied to ISCAS85 and ISCAS89 benchmark circuits. SPICE simulation results demonstrate the ability of the alignment-driven test generator to increase crosstalk-induced delays along victim paths.

In this paper a test set embedding based on accumulator driven by an odd additive constant is presented. The problem is formulated around finding the location of the test pattern in the sequence generated by the accumulator, given a odd constant C and test set T, in terms of linear Diophantine equation of two variables. We show that the search space for finding the best constant corresponding to the shortest length, is greatly reduced. Experimental results show a significant improvement in run time with practically acceptable test length.

This thesis is focused on application development for simulation lenses’ optical distortions and also for creation own patterns. In the first part are discussed common problems of optical distortion and concept of software analysis. Further is described realization and implementation of particular modules in the application. In the end is show up graphical user interface and its functionality.