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The emergence of the exascale era necessitates development of new techniques to efficiently perform high-performance scientific simulations, online data analysis and on-the-fly visualization. Critical applications like cyclone tracking and earthquake modeling require high-fidelity and high- performance simulations involving large-scale computations and generate huge amounts of data. Faster simulations and simultaneous online data analysis and visualization enable scientists provide real-time guidance to policy makers. In this thesis, we present a set of techniques for efficient high-fidelity simulations, online data analysis and visualization in environments with varying resource configurations. First, we present a strategy for improving throughput of weather simulations with multiple regions of interest. We propose parallel execution of these nested simulations based on partitioning the 2D process grid into disjoint rectangular regions associated with each subdomain. The process grid partitioning is obtained from a Huffman tree which is constructed from the relative execution times of the subdomains. We propose a novel combination of performance prediction, processor allocation methods and topology-aware mapping of the regions on torus interconnects. We observe up to 33% gain over the default strategy in weather models. Second, we propose a processor reallocation heuristic that minimizes data redistribution cost while reallocating processors in the case of dynamic regions of interest. This algorithm is based on hierarchical diffusion approach that uses a novel tree reorganization strategy. We have also developed a parallel data analysis algorithm to detect regions of interest within a domain. This helps improve performance of detailed simulations of multiple weather phenomena like depressions and clouds, thereby in- creasing the lead time to severe weather phenomena like tornadoes and storm surges. Our method is able to reduce the redistribution time by 25% over a simple partition from scratch method. We also show that it is important to consider resource constraints like I/O bandwidth, disk space and network bandwidth for continuous simulation and smooth visualization. High simulation rates on modern-day processors combined with high I/O bandwidth can lead to rapid accumulation of data at the simulation site and eventual stalling of simulations. We show that formulating the problem as an optimization problem can deter- mine optimal execution parameters for enabling smooth simulation and visualization. This approach proves beneficial for resource-constrained environments, whereas a naive greedy strategy leads to stalling and disk overflow. Our optimization method provides about 30% higher simulation rate and consumes about 25-50% lesser storage space than a naive greedy approach. We have then developed an integrated adaptive steering framework, InSt, that analyzes the combined e ect of user-driven steering with automatic tuning of application parameters based on resource constraints and the criticality needs of the application to determine the final parameters for the simulations. It is important to allow the climate scientists to steer the ongoing simulation, specially in the case of critical applications. InSt takes into account both the steering inputs of the scientists and the criticality needs of the application. Finally, we have developed algorithms to minimize the lag between the time when the simulation produces an output frame and the time when the frame is visualized. It is important to reduce the lag so that the scientists can get on-the- y view of the simulation, and concurrently visualize important events in the simulation. We present most-recent, auto-clustering and adaptive algorithms for reducing lag. The lag-reduction algorithms adapt to the available resource parameters and the number of pending frames to be sent to the visualization site by transferring a representative subset of frames. Our adaptive algorithm reduces lag by 72% and provides 37% larger representativeness than the most-recent for slow networks.

[pt] A visualização de campos vetoriais é uma componente essencial de numerosas aplicações, em particular na Visualização Científica. Porém, produzir representações de um fluxo nem sempre é uma tarefa simples, principalmente em se tratando de dados medidos, pois estes se apresentam corrompidos por ruídos. Esse trabalho apresenta uma técnica de visualização baseada em imagens auto-animadas, que expressa o movimento do fluxo à base de ilusões ópticas. A utilização de informações topológicas é proposta tanto como forma de melhorar o desempenho das técnicas existentes como na remoção de ruído, onde o conhecimento do usuário sobre o dado se torna peça fundamental no processo. / [en] Vector field visualization is an essential component of various applications, particularly in Scientific Visualization. However generating useful ow representation is not a simple task, especially when dealing with measured data which is corrupted by noise. This work presents a self-animating image visualization technique which conveys the ow movement based on optical illusions. The field s topological information is used to improve the performance of existing techniques and remove noise, where the user s knowledge of data is fundamental.

Les circuits intégrés (CI) devenant de plus en plus complexes et vulnérables face aux décharges électrostatiques (ESD pour ElectroStatic Discharge), la capacité à vérifier de manière fiable la présence de défauts de conception ESD sur des puces comptant plusieurs milliards de transistors avant tout envoi en fabrication est devenu un enjeu majeur dans l’industrie des semi-conducteurs. Des outils commerciaux automatisés de dessin électronique (EDA pour Electronic Design Automation) et leur flot de vérification associé permettent d’effectuer différents types de contrôles qui se sont révélés être efficaces pour des circuits avec une architecture classique. Cependant, ils souffrent de limitations lorsqu’ils sont confrontés à des architectures inhabituelles, dites custom. De plus, ces méthodes de vérification sont généralement effectuées tard dans le flot de conception, rendant toute rectification de dessin coûteuse en termes d’efforts correctifs et de temps. Cette thèse de doctorat propose une méthodologie de vérification ESD systématique et multi-échelle introduite dans un outil appelé ESD IP Explorer qui a été spécifiquement implémenté pour couvrir le flot de conception dans sa globalité et pour adresser des circuits dits custom. Il est composé d’un module de reconnaissance et d’un module de vérification. Le module de reconnaissance identifie tout d’abord et de manière automatisée les structures de protection ESD, embarquées sur silicium dans le circuit intégré pour améliorer leur robustesse ESD, selon un mécanisme de reconnaissance topologique. Le module de vérification convertit ensuite le réseau de protection ESD, formé des structures de protection ESD, en un graphe dirigé. Finalement, une analyse ESD quasi-statique reposant sur des algorithmes génériques issus de la théorie des graphes est effectuée sur la globalité du circuit à vérifier. Des algorithmes d’apprentissage automatique ont été employés pour prédire les comportements quasi-statiques des protections ESD à partir des paramètres d’instance de leurs composants élémentaires sous la forme d’une liste d’interconnexions. L’avantage ici est qu’aucune simulation électrique n’est requise pendant toute la durée d’exécution d’ESD IP Explorer, ce qui simplifie l’architecture de l’outil et accélère l’analyse. Les efforts d’implémentation ont été concentrés sur la compatibilité d’ESD IP Explorer avec le nœud technologique 28nm FD-SOI (pour Fully Depleted Silicon On Insulator). L’outil de vérification développé a été utilisé avec succès pour l’analyse d’un circuit incorporant des parties numériques et à signaux mixtes et comprenant plus de 1,5 milliard de transistors en seulement quelques heures. Des circuits custom qui n’ont pas pu être vérifiés au moyen d’outils de vérification traditionnels du fait de problèmes d’incompatibilité ont également pu être soumis à analyse grâce à ESD IP Explorer. / As Integrated Circuits (ICs) become more complex and susceptible to ElectroStatic Discharges (ESD), the ability to reliably verify the presence of ESD design weaknesses over a multi-billion transistor chip prior to the tape-out is a major topic in the semiconductor industry. Commercial tools dedicated to Electronic Design Automation (EDA) and related verification flows are in charge of providing checks that have been proven to be efficient for circuits with a mainstream architecture. However, they suffer limitations when confronted with custom designs. Moreover, these verification methods are often run late in the design flow, making any design re-spin costly in terms of corrective efforts and time. This Ph. D. thesis proposes a systematic and scalable ESD verification methodology embodied in a tool called ESD IP Explorer that has been specifically implemented to cover the entire design flow and to comply with custom circuit architectures. It is composed of a recognition module and a verification module. The recognition module first automatically identifies ESD protection structures, embedded in integrated circuits to enhance their ESD hardness, according to a topology-aware recognition mechanism. The verification module then converts the ESD protection network that is formed by ESD protection structures into a directed graph. There, technology-independent and graph-based verification mechanisms perform a chip-scale quasistatic ESD analysis. Machine learning algorithms have been used in order to infer the quasistatic behavior of ESD IPs from the netlist instance parameters of their primary devices. This approach has the advantage that no simulation is required during the execution of ESD IP Explorer, which makes the tool architecture simpler and improves execution times. Implementation efforts pertained to the compliance of ESD IP Explorer with the 28nm Fully Depleted Silicon On Insulator (FD-SOI) technology node. The developed verification tool has been used to successfully analyze a digital and mixed-signal circuit prototype counting more than 1.5 billion transistors in several hours, as well as custom designs that could not be analyzed by means of traditional verification tools due to incompatibility issues.