M.A. (Psychology) / The lack of research relating to the influence of self assertive behaviour on the general functioning of children can be seen as one of the most important reasons for the initiation of this study. Consequently, the goal of this investigation was mainly to evaluate the influence of a Transactional Analysis programme, 'TA for Tots' on the self assertive behaviour of a group of children. The development of social skills during childhood provides the theoretical background to the current study. The social development of the child during middle childhood with specific reference to the influence of parents and the peer group, is emphasised. In addition, relevant l.iterature is discussed relating to the therapeutic management of deficient social skills. The theoretical. orientation of Transactional. Analysis and its relation to the development of the individual personality is also discussed. The sample consisted of 32 children, who live at a children's home, and whose ages range from seven to eleven years. Subjects were selected according to specific criteria on the Children's Personali ty auestionaire. They were then randomly assigned to four groups, consisting of three experimental groups and one control. group. Two of the experimental groups were exposed to the Transactional Analysis Programme. The SUbjects in the third experimental group were only exposed to group discussions and activities, while the control group received no experimental attention. Self assertive behaviour was observed by three independent observers. The content of the programme focused on the identification of any negative thoughts, emotions and behaviour within an interpersonal context and the communicatIon thereof, which resembles the definition of self assertive behaviour

Multi-core computing is becoming ubiquitous due to the scaling limitations of single-core computing. It is inevitable that parallel programming will become the mainstream for such processors. In this paradigm shift, the concept of abstraction should not be compromised. A programming model serves as an abstraction of how programs are executed. Transactional Memory (TM) is a technique proposed to maintain lock free synchronization. Due to the simplicity of the abstraction provided by it, TM can also be used as a way of distributing parallel work, maintaining coherence and consistency. Motivated by this, at a higher level, the thesis makes three contributions and all are centred around Hardware Transactional Memory (HTM).As the first contribution, a transaction-only architecture is coupled with a ``data centric" approach, to address the scalability issues of the former whilst maintaining its simplicity. This is achieved by grouping together memory locations having similar access patterns and maintaining coherence and consistency according to the group each memory location belongs to. As the second contribution a novel technique is proposed to reduce the number of false transaction aborts which occur in a signature based HTM. The idea is to adaptively switch between cache lines and signatures to detect conflicts. That is, when a transaction fits in the L1 cache, cache line information is used to detect conflicts and signatures are used otherwise. As the third contribution, the thesis makes a case for having an exit functionality in an HTM. The objective of the proposed functionality, TM_EXIT, is to terminate a transaction without restarting or committing.

No description available.

Transactional memory (TM) is a promising lock-free synchronisation technique which offers a high-level abstract parallel programming model for future chip multiprocessor (CMP) systems. Moreover, it adapts the well-established popular paradigm of transactions and thus provides a general and flexible way to allow programs to read and modify disparate memory locations atomically as a single operation. In this thesis, we propose a general framework for validating a TM design, starting from a formal specification into a hardware implementation, with its underpinning theory and refinement. A methodology in this work starts with a high-level and executable specification model for an abstract TM with verification for various correctness conditions of concurrent transactions. This model is constructed within a flexible transition framework that allows verifying correctness of a TM system with animation. Then, we present a formal executable specification for a chip-dual single-cycle MIPS processor with a cache coherence protocol and integrate the provable TM system. Finally, we transform the dual processors with the TM from a high-level description into a Hardware Description Language (VHDL), using some proposed refinement and restriction rules. Interval Temporal Logic (ITL) and its programming language subset AnaTempura are used to build, execute and test the model, since they together provide a powerful framework supporting logical reasoning about time intervals as well as programming and simulation.

Neste trabalho apresenta-se uma avaliação do desempenho da implementação de memória transacional da linguagem Clojure, utilizada como biblioteca de sincronização para uso em conjunto com outras aplicações dentro da máquina virtual de Java. É implementada uma camada de interface entre as estruturas de dados de Clojure e o benchmark STMBench7 e são discutidos alguns aspectos que geram sobrecarga no desempenho. / In this work a performance evaluation of Clojure transactional memory implementation is presented, using it as a synchronization library to work together with other applications on Java virtual machine. It is implemented an interface layer between Clojure data structures and STMBench7 benchmark, and issues about overhead in performance are discussed.

Software transactional memory (STM) is an optimistic concurrent lock free mechanism that has the potential of positively transforming how concurrent programming is performed. STM, despite its many desirable attributes, is not yet a ubiquitous programming language feature in the commercial software domain. There are many implementation challenges with retrofitting STM into pre-existing language frameworks. Furthermore, existing software systems will also need to be refactored in order to take advantage of STM’s unique benefits. As with other time consuming and error prone refactoring processes, refactoring for STM is best done with automated tool support; it is the aim of this paper to propose such a tool. / text

Purpose: The purpose of this dissertation will be to identify a conceptual model to describe the stress and coping process among a group of elite female tennis players during a high stakes performance situation. The Transactional Model of Stress and Coping (TA model) served as the theoretical basis for this dissertation. Structural equation modeling was used to analyze the indirect effect of social support, dispositional coping, coping strategies, tennis ability and cognitive appraisal upon competitive state anxiety. Significance of the investigation: The WTA Tour, the governing body of professional tennis, has identified the priorities of promoting career longevity, development of a balanced athlete, the attainment of a profitable career for its athletes and protecting the TOUR's most valuable commodity, athlete health (AEC Report, 1995). The findings of this investigation serve to guide future interventions for managing stress and coping among elite athletes. This is one of the first investigations with this under-studied population and therefore, contributes to the available body of knowledge in stress and coping among elite athletes. Methods: Ninety-four female tennis players responded to the Competition Questionnaire during a high stakes athletic competition. Questions addressed dispositional coping strategies, current coping strategies as well as perceived competitive state anxiety and perceived sense of social support. Measurement models were used prior to construction of sub-models based upon TA model theory. Goodness of fit was assessed with significant path scores retained to construct a final conceptual model. Findings: The Competitive State Anxiety Inventory-2 was supported as a measure of competitive state anxiety. A parsimonious measure of primary appraisal and secondary appraisal was found for this elite group of athletes. Results yielded support for the strong effect of primary appraisal upon increased competitive state anxiety. In addition, both social support and secondary appraisal demonstrated a significant effect with lower competitive state anxiety. Tennis ability as measured by current rank did not have a significant effect upon appraisal, coping strategies nor competitive state anxiety. Conclusions: Based upon these results, a variation of the TA model as constructed within this investigation was found to be relevant for this elite group. The constructed conceptual model can be used to guide current and future interventions by health care practitioners that interact closely with these athletes during high stress competitive events. Implications for future interventions with this population include the need for enhancement of challenging appraisals and the need for restructuring of threatening appraisals. Though caution must be used when generalizing results, findings add to the body of knowledge regarding this under-investigated population. Future investigations could focus upon replication of results, investigation regarding the function of social support and the comparison of specific coping strategies used by subsets of athletes within this population. / text

The increasing ubiquity of chip multiprocessor machines has made the need for accessible approaches to parallel programming all the more urgent. The current state of the art, based on threads and locks, requires the programmer to use mutual exclusion to protect shared resources, enforce invariants, and maintain consistency constraints. Despite decades of research effort, this approach remains fraught with difficulty. Lock-based programming is complex and error-prone, largely due to well-known problems such as deadlock, priority inversion, and poor composability. Tradeoffs between performance and complexity for locks remain unattractive. Coarse-grain locking is simple but introduces artificial sharing, needless serialization, and yields poor performance. Fine-grain locking can address these issues, but at a significant cost in complexity and maintainability. Transactional memory has emerged as a technology with the potential to address this need for better parallel programming tools. Transactions provide the abstraction of isolated, atomic execution of critical sections. The programmer specifies regions of code which access shared data, and the system is responsible for executing that code in a way that is isolated and atomic. The programmer need not reason about locks and threads. Transactional memory removes many of the pitfalls of locking: transactions are livelock- and deadlock-free and may be composed freely. Hardware transactional memory, which is the focus of this thesis, provides an efficient implementation of the TM abstraction. This thesis explores several key aspects of supporting hardware transactional memory (HTM): operating systems support and integration, architectural, design, and implementation considerations, and programmer-transparent techniques to improve HTM performance in the presence of contention. Using and supporting HTM in an OS requires innovation in both the OS and the architecture, but enables practical approaches and solutions to some long-standing OS problems. Innovations in transactional cache coherence protocols enable HTM support in the presence of multi-level cache hierarchies, rich HTM semantics such as suspend/resume and multiple transactions per thread context, and can provide the building blocks for support of flexible contention management policies without the need to trap to software handlers. We demonstrate a programmer-transparent hardware technique for using dependences between transactions to commit conflicting transactions, and suggest techniques to allow conflicting transactions to avoid performance-sapping restarts without using heuristics such as backoff. Both mechanisms yield better performance for workloads that have significant write-sharing. Finally, in the context of the MetaTM HTM model, this thesis contributes a high-fidelity cross-design comparison of representative proposals from the literature: the result is a comprehensive exploration of the HTM design space that compares the behavior of models of MetaTM (70, 75), LogTM (58, 94), and Sun's Rock (22). / text

Neste trabalho apresenta-se uma avaliação do desempenho da implementação de memória transacional da linguagem Clojure, utilizada como biblioteca de sincronização para uso em conjunto com outras aplicações dentro da máquina virtual de Java. É implementada uma camada de interface entre as estruturas de dados de Clojure e o benchmark STMBench7 e são discutidos alguns aspectos que geram sobrecarga no desempenho. / In this work a performance evaluation of Clojure transactional memory implementation is presented, using it as a synchronization library to work together with other applications on Java virtual machine. It is implemented an interface layer between Clojure data structures and STMBench7 benchmark, and issues about overhead in performance are discussed.

No description available.