Yes / Seabed instability around a pipeline is one of the primary concerns in offshore pipeline projects. To date, most studies focus on investigating the wave/current-induced response within a porous seabed around either a fully buried pipeline or a thoroughly exposed one. In this study, unlike previous investigations, a series of comprehensive laboratory experiments are carried out in a wave flume to investigate the wave-induced pore pressures around a partially embedded pipeline in a trench layer. Measurements show that the presence of the partially buried pipeline can significantly affect the excess pore pressure in a partially backfilled trench layer, which deviates considerably from that predicted by the theoretical approach. The morphology of the trench layer accompanied with the backfill sediments, especially the deeper trench and thicker backfill (i.e.,b≥1D,e≥0.5D), provides a certain degree of resistance to seabed instability. The amplitude of excess pore pressure around the trench layer roughly exhibits a left-right asymmetric distribution along the periphery of the pipeline, and decays sharply from the upper layer of the trench to the lower region. Deeper trench depth and thicker buried layer significantly weaken the pore-water pressures in the whole trench area, thus sheltering and protecting the submarine pipeline against the transient seabed liquefaction. / The National Key research and development program of China (2017YFC1404200), the research grants of Jiangsu (BK20150804), the marine renewable energy research project of State Oceanic Administration (GHME2015GC01), Open Foundation of State Key Laboratory of Hydrology-Water Resources and Hydraulic Engineering, Hohai University (Project No: 2016491011), the Royal Academy of Engineering the Distinguished Visiting Fellowship (DVF1718-8-7)

This thesis is mainly proposed and discussed the characteristics of polycrystalline silicon thin film transistor putting forward and probing into four kinds of novel buried-oxide structures. Because of the shortcoming of the traditional polycrystalline silicon thin film transistor, like leakage current (On/Off state current), subthreshold swing, floating body effect (kink effect), self-heating effect, and short channel effect etc.. Thus, we propose and fabricate four kinds of novel structural polycrystalline silicon thin film transistors that are involved in the following, indicating to improve the critical issues of polycrystalline silicon thin film transistor mentioned above. 1. We propose and fabricate the multiple/dual trenched-body polycrystalline silicon thin film transistor. This proposed structure is demonstrated to obviously suppress the off-state leakage up to 70% reduction, comparing with the conventional device. Also, we survey the reliability of this proposed device included temperature and DC hot-carrier stress effects. We found that the trenched-body TFTs perform more rapid degradation than the conventional TFT does after the temperature and stress durations, but their electrical characteristics are still superior to the conventional counterparts. Importantly, we demonstrate that this proposed device have a dramatic potential to be a novel capacitorless 1T-DRAM, because of its large floating-body-charge storages. As the experiment, the large threshold voltage shift is examined apparently after a certain write and erase operations, leading to a manifest programming window. 2. We propose and fabricate the block-oxide polycrystalline silicon thin film transistor. This proposed structure can not only improve the leakage issue of conventional device seriously, but also avoid fluctuating threshold voltage attributed from the ultra-thin film effect. 3. We propose and fabricate the floating-body contact polycrystalline silicon thin film transistor. This structure is modified by the conventional contact window in order to effectively improve the kink effect, utilizing the bottom gate polycrystalline silicon thin film transistor. 4. Finally, we propose and simulate the non-continuous buried layer polycrystalline silicon thin film transistor. This structure built upon the field oxidation layer can effectively improve the self-heating effect and kink effect. Furthermore, this structure is simple to fabricate, practical, and completely compatible on CMOS technology.

This thesis reports on a new implementation of high quality factor (Q) copper (Cu) inductors on CMOS-grade (10-20ohm.cm) silicon (Si) substrates using a fully CMOS-compatible process. A low-temperature (less than300C) fabrication sequence is employed to reduce the loss of Si wafers at RF frequencies by trenching the Si substrate. The high aspect-ratio (30:1) trenches are subsequently bridged over or refilled with a low-loss material to close the open areas and to create a rigid low-loss island (Trenched Si Island) on which the inductors can be fabricated. The method reported here does not require air suspension of the inductors, resulting in mechanically-robust structures that are compatible with any packaging technology. The metal loss of inductors is reduced by electroplating thick (~20m) Cu layer. Fabricated inductors are characterized and modeled from S-parameter measurement. Measurement results are in good agreement with SONNET electromagnetic simulations. A one-turn 0.8nH Cu inductor fabricated on a Trenched Silicon Island (TSI) exhibits high Q of 71 at 8.75 GHz. Whereas, the identical inductor fabricated on a 20um thick silicon dioxide (SiO2) coated standard Si substrate has a maximum Q of 41 at 1.95GHz. Comparing the Q of inductors on TSI with that of other micromachined Si substrates reveals the significant effect of trenching the Si in reduction of the substrate loss. This thesis outlines the design, fabrication, characterization and modeling of spiral type Cu inductors on the TSIs.