The aggressive reduction of feature size in silicon (Si)-based complimentary metal-oxide-semiconductor (CMOS) technology has resulted in an exponential increase in computing power. Stemming from increases in device density and substantial progress in materials science and transistor design, the integrated circuit has seen continual performance improvements and simultaneous reductions in operating power (VDD). Nevertheless, existing Si-based metal-oxide-semiconductor field-effect transistors (MOSFETs) are rapidly approaching the physical limits of their scaling potential. New material innovations, such as binary group IV or ternary III-V compound semiconductors, and novel device architectures, such as the tunnel field-effect transistor (TFET), are projected to continue transistor miniaturization beyond the Si CMOS era. Unlike conventional MOSFET technology, TFETs operate on the band-to-band tunneling injection of carriers from source to channel, thereby resulting in steep switching characteristics. Furthermore, narrow bandgap semiconductors, such as germanium (Ge) and InxGa1-xAs, enhance the ON-state current and improve the switching behavior of TFET devices, thus making these materials attractive candidates for further study. Moreover, epitaxial growth of Ge on InxGa1-xAs results in tensile stress (ε) within the Ge thin-film, thereby giving device engineers the ability to tune its material properties (e.g., mobility, bandgap) via strain engineering and in so doing enhance device performance. For these reasons, this research systematically investigates the material, optical, electronic transport, and heterointerfacial properties of ε-Ge/InxGa1-xAs heterostructures grown on GaAs and Si substrates. Additionally, the influence of strain on MOS interfaces with Ge is examined, with specific application toward low-defect density ε-Ge MOS device design. Finally, vertical ε-Ge/InxGa1-xAs tunneling junctions are fabricated and characterized for the first time, demonstrating their viability for the continued development of next-generation low-power nanoelectronic devices utilizing the Ge/InxGa1-xAs material system. / Doctor of Philosophy / The aggressive scaling of transistor size in silicon-based complimentary metal-oxide-semiconductor technology has resulted in an exponential increase in integrated circuit (IC) computing power. Simultaneously, advances in materials science, transistor design, IC architecture, and microelectronics fabrication technologies have resulted in reduced IC operating power requirements. As a consequence, state-of-the-art microelectronic devices have computational capabilities exceeding those of the earliest super computers at a fraction of the demand in energy. Moreover, the low-cost, high-volume manufacturing of these microelectronic devices has resulted in their nigh-ubiquitous proliferation throughout all aspects of modern life. From social engagement to supply chain logistics, a vast web of interconnected microelectronic devices (i.e., the "Internet of Things") forms the information technology bedrock upon which 21st century society has been built. Hence, as progress in microelectronics and related fields continues to evolve, so too does their impact on an increasingly dependent world. Moore's Law, or the doubling of IC transistor density every two years, is the colloquialism used to describe the rapid advancement of the microelectronics industry over the past five decades. As mentioned earlier, parallel improvements in semiconductor technologies have spearheaded great technological change. Nevertheless, Moore's Law is rapidly approaching the physical limits of transistor scaling. Consequently, in order to continue improving IC (and therefore microelectronic device) performance, new innovations in materials and fabrication science, and transistor and IC designs are required. To that end, this research systematically investigates the material, optical, and electrical properties of novel semiconductor material systems combining elemental (e.g., Germanium) and compound (e.g., Gallium Arsenide) semiconductors. Additionally, alternative transistor design concepts are explored that leverage the unique properties of the aforementioned materials, with specific application to low-power microelectronics. Therefore, through a holistic approach towards semiconductor materials, devices, and circuit co-design, this work demonstrates, for the first time, novel transistor architectures suitable for the continued development of next-generation low-power, high-performance microelectronic devices.

The overall energy consumption of portable devices has been projected to triple over the next decade, growing to match the total power generated by the European Union and Canada by 2025. The rise of the internet-of-things (IoT) and ubiquitous and embedded computing has resulted in an exponential increase in such devices, wherein projections estimate that 50 billion smart devices will be connected and online by 2020. In order to alleviate the associated stresses placed on power generation and distribution networks, a holistic approach must be taken to conserve energy usage in electronic devices from the component to the circuit level. An effective approach to reduce power dissipation has been a continual reduction in operating voltage, thereby quadratically down-scaling active power dissipation. However, as state-of-the-art silicon (Si) complimentary metal-oxide-semiconductor (CMOS) field-effect transistors (FETs) enter sub-threshold operation in the ultra-low supply voltage regime, their drive current is noticeable degraded. Therefore, new energy-efficient MOSFETs and circuit architectures must be introduced. In this work, tunnel FETs (TFETs), which operate leveraging quantum mechanical tunneling, are investigated. A comprehensive investigation detailing electronic materials, to novel TFET device designs, to memory and logic digital circuits based upon those TFETs is provided in this work. Combined, these advances offer a computing platform that could save considerable energy and reduce power consumption in next-generation, ultra-low voltage applications. / Ph. D. / The overall energy consumption of portable devices has been projected to triple over the next decade, growing to match the total power generated by the European Union and Canada by 2025. The rise of the internet-of-things (IoT) and ubiquitous and embedded computing has resulted in an exponential increase in such devices, wherein projections estimate that 50 billion “smart” devices will be connected and “online” by 2020. In order to alleviate the associated stresses placed on power generation and distribution networks, a holistic approach must be taken to conserve energy usage in electronic devices from the component to the circuit level. An effective approach to reduce power dissipation has been a continual reduction in operating voltage, thereby quadratically down-scaling active power dissipation. However, as state-of-the-art silicon (Si) complimentary metal-oxide-semiconductor (CMOS) field-effect transistors (FETs) enter sub-threshold operation in the ultra-low supply voltage regime, their drive current is noticeable degraded. Therefore, new energy-efficient MOSFETs and circuit architectures must be introduced. In this work, tunnel FETs (TFETs), which operate leveraging quantum mechanical tunneling, are investigated. A comprehensive investigation detailing electronic materials, to novel TFET device designs, to memory and logic digital circuits based upon those TFETs is provided in this work. Combined, these advances offer a computing platform that could save considerable energy and reduce power consumption in next-generation, ultra-low voltage applications.

The Tunnel Field Effect Transistor (TFET) with sub-60mV/decade Sub-threshold slope and extremely high ION/IOFF ratio has attracted enough attention for low standby power (LSTP) applications where the battery life is very important. So far research in this area has been limited to numerical simulation and experimental analysis. It is however extremely necessary to develop compact models for TFET in order to use them in nano-scale integrated circuit design and simulation. In this work, for the first time, we develop analytical Sub-threshold slope model for n-channel double gate TFET (nDGTFET). Unlike conventional FETs, current in TFET is mainly controlled by the band-to-band tunneling mechanism at source/channel interface. As the total drain current is proportional to band-to-band generation rate, the main challenge in the present work is to find an explicit relationship between average electric field over the tunneling path and the applied gate voltage under nonlocal tunneling condition. Two dimensional Poisson’s equation (with Laplace approximation)is first solved in a rectangular coordinate system in order to obtain analytical expression for electron energy distribution over the channel region.Kane’s Model[J. Phy. Chem.Solids 12(181)1959]for band-to-band tunneling along with some analytical approximation techniques are then used to derive the expression for the Sub-threshold slope under nonlocal tunneling conditions. This Sub-threshold slope model is verified against professional numerical device simulator (MEDICI) for different device geometries. Being an asymmetric device, TFET fabrication suffers from source misalignment with gate. As the doping in source and drain-gate are different, conventional-FET-like self-aligned gate stack formation is not possible for TFET. Such misalignment, at source side, seriously degrades the performance of TFETs. To overcome this problem, in this work we explore the possibility of using “gate replacement” technique for TFET fabrication. We first develop process flow for single gate bulk nTFET, and then we extend it to n-channel double gate TFET (nDGTFET) using modified FinFET process. Good alignments between source and gate are observed with TCAD-simulations in both the cases.

<div>With the transistor dimensions scaling down to a few atoms, quantum phenomena - like quantum tunneling and entanglement - will dictate the operation and performance of the next generation of electronic devices, post-CMOS era. While quantum tunneling limits the scaling of the conventional transistor, Tunneling Field Effect Transistor (TFET) employs band-to-band tunneling for the device operation. This mechanism can reduce the sub-threshold swing (S.S.) beyond the Boltzmann's limit, which is fundamentally limited to 60 mV/dec in a conventional Si-based metal-oxide-semiconductor field-effect transistor (MOSFET). A smaller S.S. ensures TFET operation at a lower supply voltage and, therefore, at lesser power compared to the conventional Si-based MOSFET.</div><div><br></div><div>However, the low transmission probability of the band-to-band tunneling mechanism limits the ON-current of a TFET. This can be improved by reducing the body thickness of the devices i.e., using 2-Dimensional (2D) materials or by utilizing heterojunction designs. In this thesis, two promising methods are proposed to increase the ON-current; one for the 2D material TFETs, and another for the III-V heterojunction TFETs.</div><div><br></div><div>Maximizing the ON-current in a 2D material TFET by determining an optimum channel thickness, using compact models, is presented. A compact model is derived from rigorous atomistic quantum transport simulations. A new doping profile is proposed for the III-V triple heterojunction TFET to achieve a high ON-current. The optimized ON-current is 325 uA/um at a supply voltage of 0.3 V. The device design is optimized by atomistic quantum transport simulations for a body thickness of 12 nm, which is experimentally feasible.</div><div> </div><div>However, increasing the device's body thickness increases the atomistic quantum transport simulation time. The simulation of a device with a body thickness of over 12 nm is computationally intensive. Therefore, approximate methods like the mode-space approach are employed to reduce the simulation time. In this thesis, the development of the mode-space approximation in modeling the triple heterojunction TFET is also documented.</div><div><br></div><div>In addition to the TFETs, quantum computing is an emerging field that utilizes quantum phenomena to facilitate information processing. An extra chapter is devoted to the electronic structure calculations of the Si:P delta-doped layer, using the empirical tight-binding method. The calculations agree with angle-resolved photoemission spectroscopy (ARPES) measurements. The Si:P delta-doped layer is extensively used as contacts in the Phosphorus donor-based quantum computing systems. Understanding its electronic structure paves the way towards the scaling of Phosphorus donor-based quantum computing devices in the future.</div>

Technology scaling beyond Moore’s law demands cutting-edge solutions of the gate length scaling in sub-10 nm regime for low power high speed operations. Recently SOI technology has received considerable attention, however manufacturable solutions in sub-10 nm technologies are not yet known for future nanoelectronics. Therefore, to continue scalinginsub-10 nm region, new one(1D) and two dimensional(2D) “nano-materials” and engineering are expected to keep its pace. However, significant challenges must be overcome for nano-material properties in carrier transport to be useful in future silicon nanotechnology. Thus, it is very important to understand and modulate their electronic band structure and transport properties for low power nanoelectronics applications. This thesis tries to provide solutions for some problems in this area. In recent times, one dimensional Silicon nanowire has emerged as a building block for the next generation nano-electronic devices as it can accommodate multiple gate transistor architecture with excellent electrostatic integrity. However as the experimental study of various energy band parameters at the nanoscale regime is extremely challenging, usually one relies on the atomic level simulations, the results of which are at par with the experimental observations. Two such parameters are the band gap and effective mass, which are of pioneer importance for the understanding of the current transport mechanism. Although there exists a large number of empirical relations of the band gap in relaxed Silicon nanowire, however there is a growing demand for the development of a physics based analytical model to standardize different energy band parameters which particularly demands its application in TCAD software for predicting different electrical characteristics of novel devices and its strained counterpart to increase the device characteristics significantly without changing the device architecture. In the first part of this work reports the analytical modeling of energy band gap and electron transport effective mass of relaxed and strained Silicon nanowires in various crystallographic directions for future nanoelectronics. The technology scaling of gate length in beyond Moore’s law devices also demands the SOI body thickness, TSi0 which is essentially very challenging task in nano-device engineering. To overcome this circumstance, two dimensional crystals in atomically thin layered materials have found great attention for future nanolectronics device applications. Graphene, one layer of Graphite, is such 2D materials which have found potentiality in high speed nanoelectronics applications due to its several unique electronic properties. However, the zero band gap in pure Graphene makes it limited in switching device or transistor applications. Thus, opening and tailoring a band gap has become a highly pursued topic in recent graphene research. The second part of this work reports atomistic simulation based real and complex band structure properties Graphene-Boron nitride heterobilayer and Boron Nitride embedded Graphene nanoribbons which can improve the grapheme and its nanoribbon band structure properties without changing their originality. This part also reports the direct band-to-band tunneling phenomena through the complex band structures and their applications in tunnel field effect transistors(TFETs) which has emerged as a strong candidate for next generation low-stand by power(LSTP) applications due to its sub-60mV/dec Sub threshold slope(SS). As the direct band-to-band tunneling(BTBT) is improbable in Silicon(either its bulk or nanowire form), it is difficult to achieve superior TFET characteristics(i.e., very low SS and high ON cur-rent) from the Silicon TFETs. Whereas, it is explored that much high ON current and very low subthreshold slope in hybrid Graphene based TFET characteristics open a new prospect in future TFETs. The investigations on ultrathin body materials also call for a need to explore new 2D materials with finite band gap and their various nanostructures for future nanoelectronic applications in order to replace conventional Silicon. In the third part of this report, we have investigated the electronic and dielectric properties of semiconducting layered Transition metal dichalcogenide materials (MX2)(M=Mo, W;X =S, Se, Te) which has recently emerged as a promising alternative to Si as channel materials for CMOS devices. Five layered MX2 materials(exceptWTe2)in their 2D sheet and 1D nanoribbon forms are considered to study the real and imaginary band structure of thoseMX2 materials by atomistic simulations. Studying the complex dispersion properties, it is shown that all the five MX2 support direct BTBT in their monolayer sheet forms and offer an average ON current and subthresholdslopeof150 A/mand4 mV/dec, respectively. However, onlytheMoTe2 support direct BTBT in its nanoribbon form, whereas the direct BTBT possibility in MoS2 and MoSe2 depends on the number of layers or applied uniaxial strain. WX2 nanoribbons are shown to be non-suitable for efficient TFET operation. Reasonably high tunneling current in these MX2 shows that these can take advantage over conventional Silicon in future tunnel field effect transistor applications.

Technology scaling beyond Moore’s law demands cutting-edge solutions of the gate length scaling in sub-10 nm regime for low power high speed operations. Recently SOI technology has received considerable attention, however manufacturable solutions in sub-10 nm technologies are not yet known for future nanoelectronics. Therefore, to continue scalinginsub-10 nm region, new one(1D) and two dimensional(2D) “nano-materials” and engineering are expected to keep its pace. However, significant challenges must be overcome for nano-material properties in carrier transport to be useful in future silicon nanotechnology. Thus, it is very important to understand and modulate their electronic band structure and transport properties for low power nanoelectronics applications. This thesis tries to provide solutions for some problems in this area. In recent times, one dimensional Silicon nanowire has emerged as a building block for the next generation nano-electronic devices as it can accommodate multiple gate transistor architecture with excellent electrostatic integrity. However as the experimental study of various energy band parameters at the nanoscale regime is extremely challenging, usually one relies on the atomic level simulations, the results of which are at par with the experimental observations. Two such parameters are the band gap and effective mass, which are of pioneer importance for the understanding of the current transport mechanism. Although there exists a large number of empirical relations of the band gap in relaxed Silicon nanowire, however there is a growing demand for the development of a physics based analytical model to standardize different energy band parameters which particularly demands its application in TCAD software for predicting different electrical characteristics of novel devices and its strained counterpart to increase the device characteristics significantly without changing the device architecture. In the first part of this work reports the analytical modeling of energy band gap and electron transport effective mass of relaxed and strained Silicon nanowires in various crystallographic directions for future nanoelectronics. The technology scaling of gate length in beyond Moore’s law devices also demands the SOI body thickness, TSi0 which is essentially very challenging task in nano-device engineering. To overcome this circumstance, two dimensional crystals in atomically thin layered materials have found great attention for future nanolectronics device applications. Graphene, one layer of Graphite, is such 2D materials which have found potentiality in high speed nanoelectronics applications due to its several unique electronic properties. However, the zero band gap in pure Graphene makes it limited in switching device or transistor applications. Thus, opening and tailoring a band gap has become a highly pursued topic in recent graphene research. The second part of this work reports atomistic simulation based real and complex band structure properties Graphene-Boron nitride heterobilayer and Boron Nitride embedded Graphene nanoribbons which can improve the grapheme and its nanoribbon band structure properties without changing their originality. This part also reports the direct band-to-band tunneling phenomena through the complex band structures and their applications in tunnel field effect transistors(TFETs) which has emerged as a strong candidate for next generation low-stand by power(LSTP) applications due to its sub-60mV/dec Sub threshold slope(SS). As the direct band-to-band tunneling(BTBT) is improbable in Silicon(either its bulk or nanowire form), it is difficult to achieve superior TFET characteristics(i.e., very low SS and high ON cur-rent) from the Silicon TFETs. Whereas, it is explored that much high ON current and very low subthreshold slope in hybrid Graphene based TFET characteristics open a new prospect in future TFETs. The investigations on ultrathin body materials also call for a need to explore new 2D materials with finite band gap and their various nanostructures for future nanoelectronic applications in order to replace conventional Silicon. In the third part of this report, we have investigated the electronic and dielectric properties of semiconducting layered Transition metal dichalcogenide materials (MX2)(M=Mo, W;X =S, Se, Te) which has recently emerged as a promising alternative to Si as channel materials for CMOS devices. Five layered MX2 materials(exceptWTe2)in their 2D sheet and 1D nanoribbon forms are considered to study the real and imaginary band structure of thoseMX2 materials by atomistic simulations. Studying the complex dispersion properties, it is shown that all the five MX2 support direct BTBT in their monolayer sheet forms and offer an average ON current and subthresholdslopeof150 A/mand4 mV/dec, respectively. However, onlytheMoTe2 support direct BTBT in its nanoribbon form, whereas the direct BTBT possibility in MoS2 and MoSe2 depends on the number of layers or applied uniaxial strain. WX2 nanoribbons are shown to be non-suitable for efficient TFET operation. Reasonably high tunneling current in these MX2 shows that these can take advantage over conventional Silicon in future tunnel field effect transistor applications.