Class of 2016 Abstract / Objectives: To verify a set of translated medication labels in consultation with native speakers of non-English languages, specifically for this study: Amharic, Arabic, Chinese (Mandarin), Somali, Spanish, Tigrinya, and Vietnamese. Methods: Native speakers of target languages were recruited from academic and community organizations in the Tucson area. Participants were asked to review a set of translated directions and complete a survey regarding the validity and comprehensibility of the translations. In some cases, a short interview was used to clarify any comments or corrections made by the participants. Results: Surveys were completed by 23 participants, 12 men and 11 women, covering seven languages, with an uneven distribution between languages. Directions in Somali were the least problematic, with relatively strong agreement between respondents. Amharic directions were rated poorly and scored consistently worse than the overall average. Tigrinya had the most variation between respondents compared to other languages. Chinese, Spanish, and Vietnamese all received rather high scores, but analysis is complicated by a small sample size for each. Among responses to the open-ended questions, comments regarding word choice were the most common, for various reasons. Conclusions: We were able to validate some of the provided translations, but found that certain languages posed more problems than others, and these translations would need to undergo further review before they can be reliably used in clinical practice.

Proof-carrying code is an application of software verification techniques to the problem of ensuring the safety of mobile code. However, previous proof-carrying code systems have assumed that mobile code will faithfully execute the instructions of the program. Realistic implementations of computing systems are susceptible to probabilistic behaviours that can alter the execution of a program in ways that can result in corruption or security breaches. We investigate the use of a probabilistic bytecode language to model deterministic programs that are executed on probabilistic computing systems. To model probabilistic safety properties, a probabilistic logic is adapted to out bytecode instruction language, and soundness is proven. A sketch of a completeness proof of the logic is also shown.

Verification is a process that checks whether a program G, implemented by a devel- oper, correctly complies with the corresponding requirement specifications. A verifier, whose interests may be different from the developer, will conduct such verification on G. However, as the developer and the verifier distrust each other probably, either of them may exhibit harmful behavior and take advantage of the verification. Generally, the developer hopes to protect the content privacy of the program, while the verifier wants to conduct effective verification to detect the possible errors. Therefore, a ques- tion inevitably arises: How to conduct an effective and efficient kind of verification, without breaking the security requirements of the two parties? We treat verification as a process akin to testing, i.e. verifying the design with test cases and checking the results. In order to make the verification more effective, we get rid of the limitations in traditional testing approaches, like black-box and white-box testing, and propose the “partial white-box verification”. Taking circuits as the description means, we regard the program as a circuit graph. Making the structure of the graph public, we manage to make the verification process in such a graph partially white-box. Via garbled circuits, commitment schemes and other techniques, the security requirements in such verification are guaranteed. / Thesis / Master of Science (MSc)

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International Telemetering Conference Proceedings / October 25-28, 1993 / Riviera Hotel and Convention Center, Las Vegas, Nevada / This paper provides a brief history of the role strategic ballistic missile telemetry has played in U.S.-Soviet and Russian arms control relations from the first Strategic Arms Limitation Treaty (SALT I) through the second Strategic Arms Reduction Treaty (START II).

This dissertation documents two contributions to automating the formal verification of hardware – particularly memory-intensive circuits – by Symbolic Trajectory Evaluation (STE), a model checking technique based on symbolic simulation over abstract sets of states. The contributions focus on improvements to the use of BDD-based STE, which uses binary decision diagrams internally. We introduce a solution to one of the major hurdles in using STE: finding suitable abstractions. Our work has produced the first known algorithm that addresses this problem by automatically discovering good, non-trivial abstractions. These abstractions are computed from the specification, and essentially encode partial input combinations sufficient for determining the specification’s output value. They can then be used to verify whether the hardware model meets its specification using a technique based on and significantly extending previous work by Melham and Jones [2]. Moreover, we prove that our algorithm delivers correct results by construction. We demonstrate that the abstractions received by our algorithm can greatly reduce verification costs with three example hardware designs, typical of the kind of problems faced by the semiconductor design industry. We further propose a refinement method for abstraction schemes when over- abstraction occurs, i.e., when the abstraction hides too much information of the original design to determine whether it meets its specification. The refinement algorithm we present is based on previous work by Chockler et al. [3], which selects refinement candidates by approximating which abstracted input is likely the biggest cause of the abstraction being unsuitable. We extend this work substantially, concentrating on three aspects. First, we suggest how the approach can also work for much more general abstraction schemes. This enables refining any abstraction allowed in STE, rather than just a subset. Second, Chockler et al. describe how to refine an abstraction once a refinement candidate has been identified. We present three additional variants of refining the abstraction. Third, the refinement at its core depends on evaluating circuit logic gates. The previous work offered solutions for NOT- and AND-gates. We propose a general approach to evaluating arbitrary logic gates, which improves the selection process of refinement candidates. We show the effectiveness of our work by automatically refining an abstraction for a content-addressable memory that exhibits over-abstraction, and by evaluating some common logic gates. These two contributions can be used independently to help automate the hard- ware verification by STE, but they also complement each other. To show this, we combine both algorithms to create a fully automatic abstraction discovery and refinement loop. The only inputs required are the hardware design and the specification, which the design should meet. While only small circuits could be verified completely automatically, it clearly shows that our two contributions allow the construction of a verification framework that does not require any user interaction.

Este trabalho propõe o desenvolvimento de uma metodologia para a verificação circuitos integrados de sinais mistos de uso em sistemas de comunicação que operem em modo simplex. Deseja-se aproveitar as características inversas de recepção e transmissão para otimizar o processo de verificação. Para o desenvolvimento desta metodologia de verificação, teve-se como objetivo estudar metodologias de verificação de circuitos integrados de sinais mistos existentes e sua evolução, as quais têm garantido cada vez mais a funcionalidade de circuitos integrados que são compostos por blocos analógicos e digitais. A metodologia é aplicada a um dos circuitos que compõem um sistema otimizado de transmissão de dados via satélite (Transponder para Satélite). O sistema de transmissão de dados via satélite, foco do trabalho, é composto por receptores, transmissores e conversores analógico digital e um Processador Digital de Sinais - Digital Signal Processing (DSP), todos desenvolvidos em hardware. A metodologia de verificação compreende no desenvolvimento de uma estrutura de verificação capaz de estimular os blocos digitais e analógicos com o objetivo de garantir a funcionalidade de cada um dos componentes do IP Transponder. Em uma etapa seguinte, foi possível estimular o IP Transponder de forma integrada, no que se refere aos os blocos digitais e analógicos, assim como os de transmissão e recepção. Ressalta-se ainda que todo o desenvolvimento foi realizado em alto nível, ou seja, todas as características e propriedades foram observadas utilizando-se somente simuladores para garantir a funcionalidade do circuito integrado de sinais mistos que compõe o IP Transponder para satélite. / This work proposes the development of a verification methodology, used during the verification process of a mixed signal integrated circuit, which represents a communication system operating in simplex mode. In order to optimize the verification process, reverse reception and transmission will be used. With the intention of developing our verification methodology, a study on other methodologies used for the verification of mixed signals integrated circuits and the evolution of such methodologies was carried out. The proposed methodology has been applied in an advanced circuit used to establish data transmission by satellite (Transponder for Satellite). The targeted data transmission system is composed by analog receptor and transmitter, analog to digital converters and a digital signal-processing unit, all developed in hardware. The verification methodology consists of two steps: first, the development of a verification structure that are able to stimulate digital and analog blocks in order to guarantee the functionality of each system component. In a following step, the developed verification environment provides the stimulation for all the Transponder IP (digital and analog blocks), and for transmission and reception blocks as well. The verification process development was performed in high level, meaning all the characteristics and properties has been observed using only simulators with the purpose of guarantee the functionality of the mixed signal integrated circuit that composes the satellite Transponder IP.

Functional verification is a critical problem facing the semiconductor industry: hardware designs are extremely complex and highly optimized, and even a single bug in deployed systems can cost more than $10 billion. We focus on the verification of pipelining, a key optimization that appears extensively in hardware systems such as microprocessors, multicore systems, and cache coherence protocols. Existing techniques for verifying pipelined machines either consume excessive amounts of time, effort, and resources, or are not applicable at the bit-level, the level of abstraction at which commercial systems are designed and functionally verified. We present a highly automated, efficient, compositional, and scalable refinement-based approach for the verification of bit-level pipelined machines. Our contributions include: (1) A complete compositional reasoning framework based on refinement. Our notion of refinement guarantees that pipelined machines satisfy the same safety and liveness properties as their instruction set architectures. In addition, our compositional framework can be used to decompose correctness proofs into smaller, more manageable pieces, leading to drastic reductions in verification times and a high-degree of scalability. (2) The development of ACL2-SMT, a verification system that integrates the popular ACL2 theorem prover (winner of the 2005 ACM Software System Award) with decision procedures. ACL2-SMT allows us to seamlessly take advantage of the two main approaches to hardware verification: theorem proving and decision procedures. (3) A proof methodology based on our compositional reasoning framework and ACL2-SMT that allows us to reduce the bit-level verification problem to a sequence of highly automated proof steps. (4) A collection of general-purpose refinement maps, functions that relate pipelined machine states to instruction set architecture states. These refinement maps provide more flexibility and lead to increased verification efficiency. The effectiveness of our approach is demonstrated by verifying various pipelined machine models, including a bit-level, Intel XScale inspired processor that implements 593 instructions and includes features such as branch prediction, precise exceptions, and predicated instruction execution.

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Este trabalho propõe o desenvolvimento de uma metodologia para a verificação circuitos integrados de sinais mistos de uso em sistemas de comunicação que operem em modo simplex. Deseja-se aproveitar as características inversas de recepção e transmissão para otimizar o processo de verificação. Para o desenvolvimento desta metodologia de verificação, teve-se como objetivo estudar metodologias de verificação de circuitos integrados de sinais mistos existentes e sua evolução, as quais têm garantido cada vez mais a funcionalidade de circuitos integrados que são compostos por blocos analógicos e digitais. A metodologia é aplicada a um dos circuitos que compõem um sistema otimizado de transmissão de dados via satélite (Transponder para Satélite). O sistema de transmissão de dados via satélite, foco do trabalho, é composto por receptores, transmissores e conversores analógico digital e um Processador Digital de Sinais - Digital Signal Processing (DSP), todos desenvolvidos em hardware. A metodologia de verificação compreende no desenvolvimento de uma estrutura de verificação capaz de estimular os blocos digitais e analógicos com o objetivo de garantir a funcionalidade de cada um dos componentes do IP Transponder. Em uma etapa seguinte, foi possível estimular o IP Transponder de forma integrada, no que se refere aos os blocos digitais e analógicos, assim como os de transmissão e recepção. Ressalta-se ainda que todo o desenvolvimento foi realizado em alto nível, ou seja, todas as características e propriedades foram observadas utilizando-se somente simuladores para garantir a funcionalidade do circuito integrado de sinais mistos que compõe o IP Transponder para satélite. / This work proposes the development of a verification methodology, used during the verification process of a mixed signal integrated circuit, which represents a communication system operating in simplex mode. In order to optimize the verification process, reverse reception and transmission will be used. With the intention of developing our verification methodology, a study on other methodologies used for the verification of mixed signals integrated circuits and the evolution of such methodologies was carried out. The proposed methodology has been applied in an advanced circuit used to establish data transmission by satellite (Transponder for Satellite). The targeted data transmission system is composed by analog receptor and transmitter, analog to digital converters and a digital signal-processing unit, all developed in hardware. The verification methodology consists of two steps: first, the development of a verification structure that are able to stimulate digital and analog blocks in order to guarantee the functionality of each system component. In a following step, the developed verification environment provides the stimulation for all the Transponder IP (digital and analog blocks), and for transmission and reception blocks as well. The verification process development was performed in high level, meaning all the characteristics and properties has been observed using only simulators with the purpose of guarantee the functionality of the mixed signal integrated circuit that composes the satellite Transponder IP.