IMT-2000 in 1999 has adopted ATM as the backbone of the wireless network. The future W-CDMA will improve the bandwidth of wireless network to 384kb/s, even to 2Mb/s at some special area or indoor environment. Therefore, it

Understanding the cancer pathology and develop effective treatment strategies play significant roles in improving cancer survival rates. In this thesis, evaluations of mathematical modeling and simulation were studied and presented. Colorectal system was investigated from gene and cell levels. The Hardware Descriptive Language (HDL) package and codes were developed to simulate the cancer models. Representative codes and figures were illustrated. Results suggest that the HDL is an effective method to conduct the modeling and simulation of cancers. It is essential to develop advanced technology such as HDL modeling and simulation to improve our understandings to fight cancer and save lives.

Since the introduction of Complementary-Metal-Oxide-Semiconductor (CMOS) technology, the chip industry has enjoyed many benefits of transistor feature size scaling, including higher speed and device density and improved energy efficiency. However, in the recent years, the IC designers have encountered a few roadblocks, namely reaching the physical limits of scaling and also increased device leakage which has resulted in a slow-down of supply voltage and power density scaling. Therefore, there has been an extensive hunt for alternative circuit architectures and switching devices that can alleviate or eliminate the current crisis in the semiconductor industry. The Nano-Electro-Mechanical (NEM) relay is a promising alternative switch that offers zero leakage and abrupt turn-on behaviour. Even though these devices are intrinsically slower than CMOS transistors, new circuit design techniques tailored for the electromechanical properties of such devices can be leveraged to design medium performance, ultra-low power integrated circuits. In this thesis, we deal with a new generation of such devices that is built in the back end of line (BEOL) CMOS process and is an ideal option for full integration with current CMOS transistor technology. Simulation and verification at the circuit and system level is a critical step in the design flow of microelectronic circuits, and this is especially important for new technologies that lack the standard design infrastructure and well-known verification platforms. Although most of the physical and electrical properties of NEM structures can be simulated using standard electronic automation software, there is no report of a reliable behavioural model for NEMS switches that enable large circuit simulations. In this work, we present an optimised model of a BEOL nano relay that encompasses all the electromechanical characteristics of the device and is robust and lightweight enough for VLSI applications that require simulation of thousands of devices. To verify the performance of the proposed model, complex logic circuits built exclusively with relays, and also, hybrid CMOS-NEM circuits are simulated and verified. Finally, these novel topologies are reviewed and discussed as low-power alternatives to current CMOS topologies.

Dissertação (Mestrado em Engenharia Elétrica) - Centro Universitário FEI, São Bernardo do Campo, 2018

Tese de mestrado integrado. Engenharia Electrotécnica e de Computadores (Telecomunicações). Universidade do Porto. Faculdade de Engenharia. 2010

The market for Insulated Gate Bipolar Transistor (IGBT) is growing and there is a need for techniques to improve the design, modeling and simulation of IGBT. In this thesis, we first developed a new method to optimize the layout and dimensions of IGBT circuits based on device simulation and combinatorial optimization. Our method leads to the optimal IGBT layout consisting of hexagons, which is 6 % more efficient in terms of performance (current per unit area) over that of squares, and up to 80 % more efficient than rectangles. We also explored several techniques to reduce the time used for device simulation. In particular, we developed an accurate Verilog-A description based on the Hefner model. For transient simulation, the time used by SPICE on the Verilog-A model is only 1/10000 of that used by device simulation on the device structure. The SPICE results, though contain some inaccuracies in the details, match device simulation in the general trend. Due to the effectiveness and efficiency of our methods, we propose their application in designing better power electronic circuits and shorter turn-around time.

This thesis develops a hardware circuit implementation of a novel algorithm for reducing a SRM drives input current ripple or equivalently to improve the SRM drives input power quality. The algorithm requires the SRMs phase current to follow a trapezoidal trajectory relative to the rotors position with the magnitude of the current dependent on the desired average torque. This thesis deals with the generation of the required current command that is the input to a separate analog current regulator that forces the SRMs current to follow the generated current command. The final circuit design must be capable of operating at 200C to be part of a high temperature aircraft actuator. In this thesis, room temperature hardware is used to emulate and verify the high temperature design. Both a high temperature microcontroller based design and a high temperature gate array based design are considered with the high temperature gate array based design being chosen. Ultimately, a standard room temperature Xilinx FPGA is chosen to emulate the high temperature gate array. The FPGA is programmed using Verilog HDL and the code is downloaded into the chip using Xilinx ISE software. The experimentally generated output is validated by comparing it with simulation results from a detailed Simulink model of the complete drive system.

This thesis is devoted to the investigation of prioritization mechanism for web based anomaly detection. We propose a hardware realization of parallel binary heap as an application of web based anomaly prioritization. The heap is implemented in pipelined fashion in FPGA platform. The propose design takes O(1) time for all operations by ensuring minimum waiting time between two consecutive operations. We present the various design issues and hardware complexity. We explicitly analyze the design trade-offs of the proposed priority queue implementations.

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