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Ce travail présente une évaluation des performances des transistors à effet de champ à base de graphène (GFET) grâce à des simulations électriques des modèles compact dédiés à des applications à haute fréquence. Les transistors à base de graphène sont parmi les nouvelles technologies et sont des candidats prometteurs pour de futures applications à hautes performances dans le cadre du plan d’action « au-delà du transistor CMOS ». Dans ce contexte, cette thèse présente une évaluation complète des transistors à base de graphène tant au niveau du dispositif que du circuit grâce au développement de modèles compacts précis pour des GFETs, de l’analyse de la fiabilité, en étudiant les mécanismes critiques de dégradation des GFETs, et de la conception des architectures de circuits basés sur des GFETs.Dans cette thèse nous présentons, à l’aide de certaines notions bien particulières de la physique, un modèle compact grand signal des transistors FET à double grille à base de graphène monocouche. Ainsi, en y incluant une description précise des capacités de grille et de l’environnement électromagnétique (EM), ce travail étend également les aptitudes de ce modèle à la simulation RF. Sa précision est évaluée en le comparant à la fois avec un modèle numérique et avec des mesures de différentes technologies GFET. Par extension, un modèle grand signal pour les transistors FET à double grille à base de graphène bicouche est présenté. Ce modèle considère la modélisation de l’ouverture et de la modulation de la bande interdite (bandgap) dues à la polarisation de la grille. La polyvalence et l’applicabilité de ces modèles compacts des GFETs monocouches et bicouches ont été évalués en étudiant les GFETs avec des altérations structurelles.Les aptitudes du modèle compact sont encore étendues en incluant des lois de vieillissement qui décrivent le piégeage de charges et la génération d’états d’interface qui sont responsables de la dégradation induite par les contraintes de polarisation. Enfin, pour évaluer les aptitudes du modèle compact grand signal développé, il a été implémenté au niveau de différents circuits afin de prédire les performances par simulations. Les trois architectures de circuits utilisées étaient un amplificateur triple mode, un circuit amplificateur et une architecture de circuit « balun ». / This work presents an evaluation of the performances of graphene-based Field-Effect Transistors (GFETs) through electrical compact model simulation for high-frequency applications. Graphene-based transistors are one of the novel technologies and promising candidates for future high performance applications in the beyond CMOS roadmap. In that context, this thesis presents a comprehensive evaluation of graphene FETs at both device and circuit level through development of accurate compact models for GFETs, reliability analysis by studying critical degradation mechanisms of GFETs and design of GFET-based circuit architectures.In this thesis, an accurate physics-based large-signal compact model for dual-gate monolayer graphene FET is presented. This work also extends the model capabilities to RF simulation by including an accurate description of the gate capacitances and the electro-magnetic environment. The accuracy of the developed compact model is assessed by comparison with a numerical model and with measurements from different GFET technologies.In continuation, an accurate large-signal model for dual-gate bilayer GFETs is presented. As a key modeling feature, the opening and modulation of an energy bandgap through gate biasing is included to the model. The versatility and applicability of the monolayer and bilayer GFET compact models are assessed by studying GFETs with structural alterations.The compact model capabilities are further extended by including aging laws describing the charge trapping and the interface state generation responsible for bias-stress induced degradation.Lastly, the developed large-signal compact model has been used along with EM simulations at circuit level for further assessment of its capabilities in the prediction of the performances of three circuit architectures: a triple-mode amplifier, an amplifier circuit and a balun circuit architecture.

This report presents an implementation of the software part in a software definedradio. The radio is not entirely implemented in software and therefore there arecertain limitations on the received signal. The parts implemented are oscillator,decimation filter, carrier synchronization, time synchronization, package detection,and demodulation. Different algorithms were tested for the different partsto measure the power consumption. To understand how the number of bits usedto represent the signal affects the power consumption, the number of bits wasreduced from 20 bits to 10 bits. This reduction reduced the power consumptionfrom 2.57mW to 1.89mW. A small change in the choice of algorithms was thenmade which reduced the power consumption to 1.86mW. Then the clock rate wasreduced for some parts of the system which reduced the power consumption to1.05mW.

Tese de mestrado integrado. Engenharia Electrotécnica e de Computadores (Major Telecomunicações). Faculdade de Engenharia. Universidade do Porto. 2009

We propose in this paper an algebraic approach to hard-ware/software partitioning in Verilog Hardware Description Language (HDL). We explore a collection of algebraic laws for Verilog programs, from which we design a set of syntax-based algebraic rules to conduct hardware/software partitioning. The co-specification language and the target hardware and software description languages are specific subsets of Verilog. Through this, we confirm successful verification for the correctness of the partitioning process by an algebra of Verilog. Facilitated by Verilog’s rich features, we have also successfully studied hw/sw partitioning for environment-driven systems. / Singapore-MIT Alliance (SMA)

The contribution of this thesis is two-fold: an on-chip interconnection architecture designed specifically for multi-core processors and a tool framework that simplifies the process of designing a multi-core processor. Both contributions primarily target ASIC fabrication, though prototyping on an FPGA is also supported. SG-Multi, the on-chip interconnection architecture, distinguishes itself from other interconnection architectures by emphasizing universal adaptability; that is, a primary design goal is to ensure compatibility with industry-supplied cores originally intended for other architectures. This goal is achieved through the use of bus adapters and without introducing clock cycle latency. SG-Multi is a multi-bus architecture that uses slave-side arbitration and supports multiple simultaneous transactions between independent devices. All transactions are pipelined in two stages, an address phase and a data phase, and for improved performance slave devices must signal their status for a given clock cycle at the beginning of that cycle. SG-Multi Designer, the tool framework which builds systems that use SG-Multi, provides a higher level of abstraction compared to other competing system-building solutions; the set of components with which a designer must be concerned is much more limited, and low-level details such as hardware interface compatibility are removed from active consideration. Experimental results demonstrate that the hardware cost of using SG-Multi is reasonable compared to using a processor's native bus architecture, although the current implementation of arbitration is identifiable as an area for future improvement. It is also shown that SG-Multi is scalable; the reference systems grow linearly with respect to the number of cores when tested for ASIC fabrication and slightly sublinearly when tested for FPGA prototyping, and the maximum achievable clock frequency remains almost constant as the number of cores grows beyond four. Because the reference systems tested are an accurate reflection of the types of systems SG-Multi Designer produces, it is concluded that the abstraction model used by SG-Multi Designer does not over-simplify the design process in a way that causes excessive performance degradation or increased hardware resource consumption.

Es wurden verschieden Kodierungsarten fuer FSMs untersucht, schwerpunktmaessig Gray Code und andere Arten der hazardfreien Kodierung. Ein spezieller Kodierungsalgorithmus zur hazardfreien Kodierung wurde entwickelt und in eine Entwurfsumgebung implementiert. Ein weitere Schwerpunkt der Arbeit sind Codegeneratoren, die eine Verhaltensbeschreibung der FSM in Verilog oder in VHDL erzeugen.

Rotor Position information is essential in the operation of the Switched Reluctance Motor (SRM) for properly controlling its phase currents. This thesis uses Field Programmable Gate Array (FPGA) technology to implement a method to estimate the SRMs rotor position using the inverse inductance value of the SRMs phases. The estimated rotor position is given as input to the Commutator circuit, also implemented in the FPGA, to determine when torque-producing currents should be input in the SRM phase windings. The Estimator and Commutator design is coded using Verilog HDL and is simulated using Xilinx tools. This circuit is implemented on a Xilinx Virtex XCV800 FPGA system. The experimentally generated output is validated by comparing it with simulation results from a Simulink model of the Estimator. The performance of the FPGA based SRM rotor position estimator in terms of calculation time is compared to a digital signal processor (DSP) implementation of the same position estimator algorithm. It is found that the FPGA rotor position Estimator with a 5MHz clock can update its rotor position estimate every 7s compared to an update time of 50s for a TMS320C6701-150 DSP implementation using a commercial DSP board. This is a greater than 7 to one reduction in the update time.

The contribution of this thesis is two-fold: an on-chip interconnection architecture designed specifically for multi-core processors and a tool framework that simplifies the process of designing a multi-core processor. Both contributions primarily target ASIC fabrication, though prototyping on an FPGA is also supported. SG-Multi, the on-chip interconnection architecture, distinguishes itself from other interconnection architectures by emphasizing universal adaptability; that is, a primary design goal is to ensure compatibility with industry-supplied cores originally intended for other architectures. This goal is achieved through the use of bus adapters and without introducing clock cycle latency. SG-Multi is a multi-bus architecture that uses slave-side arbitration and supports multiple simultaneous transactions between independent devices. All transactions are pipelined in two stages, an address phase and a data phase, and for improved performance slave devices must signal their status for a given clock cycle at the beginning of that cycle. SG-Multi Designer, the tool framework which builds systems that use SG-Multi, provides a higher level of abstraction compared to other competing system-building solutions; the set of components with which a designer must be concerned is much more limited, and low-level details such as hardware interface compatibility are removed from active consideration. Experimental results demonstrate that the hardware cost of using SG-Multi is reasonable compared to using a processor's native bus architecture, although the current implementation of arbitration is identifiable as an area for future improvement. It is also shown that SG-Multi is scalable; the reference systems grow linearly with respect to the number of cores when tested for ASIC fabrication and slightly sublinearly when tested for FPGA prototyping, and the maximum achievable clock frequency remains almost constant as the number of cores grows beyond four. Because the reference systems tested are an accurate reflection of the types of systems SG-Multi Designer produces, it is concluded that the abstraction model used by SG-Multi Designer does not over-simplify the design process in a way that causes excessive performance degradation or increased hardware resource consumption.