Ce travail présente une évaluation des performances des transistors à effet de champ à base de graphène (GFET) grâce à des simulations électriques des modèles compact dédiés à des applications à haute fréquence. Les transistors à base de graphène sont parmi les nouvelles technologies et sont des candidats prometteurs pour de futures applications à hautes performances dans le cadre du plan d’action « au-delà du transistor CMOS ». Dans ce contexte, cette thèse présente une évaluation complète des transistors à base de graphène tant au niveau du dispositif que du circuit grâce au développement de modèles compacts précis pour des GFETs, de l’analyse de la fiabilité, en étudiant les mécanismes critiques de dégradation des GFETs, et de la conception des architectures de circuits basés sur des GFETs.Dans cette thèse nous présentons, à l’aide de certaines notions bien particulières de la physique, un modèle compact grand signal des transistors FET à double grille à base de graphène monocouche. Ainsi, en y incluant une description précise des capacités de grille et de l’environnement électromagnétique (EM), ce travail étend également les aptitudes de ce modèle à la simulation RF. Sa précision est évaluée en le comparant à la fois avec un modèle numérique et avec des mesures de différentes technologies GFET. Par extension, un modèle grand signal pour les transistors FET à double grille à base de graphène bicouche est présenté. Ce modèle considère la modélisation de l’ouverture et de la modulation de la bande interdite (bandgap) dues à la polarisation de la grille. La polyvalence et l’applicabilité de ces modèles compacts des GFETs monocouches et bicouches ont été évalués en étudiant les GFETs avec des altérations structurelles.Les aptitudes du modèle compact sont encore étendues en incluant des lois de vieillissement qui décrivent le piégeage de charges et la génération d’états d’interface qui sont responsables de la dégradation induite par les contraintes de polarisation. Enfin, pour évaluer les aptitudes du modèle compact grand signal développé, il a été implémenté au niveau de différents circuits afin de prédire les performances par simulations. Les trois architectures de circuits utilisées étaient un amplificateur triple mode, un circuit amplificateur et une architecture de circuit « balun ». / This work presents an evaluation of the performances of graphene-based Field-Effect Transistors (GFETs) through electrical compact model simulation for high-frequency applications. Graphene-based transistors are one of the novel technologies and promising candidates for future high performance applications in the beyond CMOS roadmap. In that context, this thesis presents a comprehensive evaluation of graphene FETs at both device and circuit level through development of accurate compact models for GFETs, reliability analysis by studying critical degradation mechanisms of GFETs and design of GFET-based circuit architectures.In this thesis, an accurate physics-based large-signal compact model for dual-gate monolayer graphene FET is presented. This work also extends the model capabilities to RF simulation by including an accurate description of the gate capacitances and the electro-magnetic environment. The accuracy of the developed compact model is assessed by comparison with a numerical model and with measurements from different GFET technologies.In continuation, an accurate large-signal model for dual-gate bilayer GFETs is presented. As a key modeling feature, the opening and modulation of an energy bandgap through gate biasing is included to the model. The versatility and applicability of the monolayer and bilayer GFET compact models are assessed by studying GFETs with structural alterations.The compact model capabilities are further extended by including aging laws describing the charge trapping and the interface state generation responsible for bias-stress induced degradation.Lastly, the developed large-signal compact model has been used along with EM simulations at circuit level for further assessment of its capabilities in the prediction of the performances of three circuit architectures: a triple-mode amplifier, an amplifier circuit and a balun circuit architecture.

abstract: This work focuses on the existence of multiple resistance states in a type of emerging non-volatile resistive memory device known commonly as Programmable Metallization Cell (PMC) or Conductive Bridge Random Access Memory (CBRAM), which can be important for applications such as multi-bit memory as well as non-volatile logic and neuromorphic computing. First, experimental data from small signal, quasi-static and pulsed mode electrical characterization of such devices are presented which clearly demonstrate the inherent multi-level resistance programmability property in CBRAM devices. A physics based analytical CBRAM compact model is then presented which simulates the ion-transport dynamics and filamentary growth mechanism that causes resistance change in such devices. Simulation results from the model are fitted to experimental dynamic resistance switching characteristics. The model designed using Verilog-a language is computation-efficient and can be integrated with industry standard circuit simulation tools for design and analysis of hybrid circuits involving both CMOS and CBRAM devices. Three main circuit applications for CBRAM devices are explored in this work. Firstly, the susceptibility of CBRAM memory arrays to single event induced upsets is analyzed via compact model simulation and experimental heavy ion testing data that show possibility of both high resistance to low resistance and low resistance to high resistance transitions due to ion strikes. Next, a non-volatile sense amplifier based flip-flop architecture is proposed which can help make leakage power consumption negligible by allowing complete shutdown of power supply while retaining its output data in CBRAM devices. Reliability and energy consumption of the flip-flop circuit for different CBRAM low resistance levels and supply voltage values are analyzed and compared to CMOS designs. Possible extension of this architecture for threshold logic function computation using the CBRAM devices as re-configurable resistive weights is also discussed. Lastly, Spike timing dependent plasticity (STDP) based gradual resistance change behavior in CBRAM device fabricated in back-end-of-line on a CMOS die containing integrate and fire CMOS neuron circuits is demonstrated for the first time which indicates the feasibility of using CBRAM devices as electronic synapses in spiking neural network hardware implementations for non-Boolean neuromorphic computing. / Dissertation/Thesis / Doctoral Dissertation Electrical Engineering 2015

Passive components are indispensable in the design and development of microchips for high-frequency applications. Inductors in particular are used frequently in radio frequency (RF) IC's such as low-noise amplifiers and oscillators. High performance inductor has become one of the critical components for voltage controlled oscillator (VCO) design, for its quality factor (Q) value directly affects the VCO phase noise. The optimization of inductor layout can improve its performance, but the improvement is limited by selected technology. Inductor performance is bounded by the thin routing metal and small distance from lossy substrate. On the other hand, the in-accurate inductor modeling further limits the optimization process. The on-chip inductor has been an important research topic since it was first proposed in early 1990's. Significant amount of study has been accomplished and reported in literature; whereas some methods have been used in industry, but not released to public. It is of no doubt that a comprehensive solution is not exist yet. A comprehensive study of previous will be first address. Later author will point out the in-adequacy of skin effect and proximity effect as cause of current crowding in the inductor metal. A model method embedded with new explanation of current crowding is proposed and its applicability in differential inductor and balun is validated. This study leads to a robust optimization routine to improve inductor performance without any addition technology cost and development.

abstract: The non-quasi-static (NQS) description of device behavior is useful in fast switching and high frequency circuit applications. Hence, it is necessary to develop a fast and accurate compact NQS model for both large-signal and small-signal simulations. A new relaxation-time-approximation based NQS MOSFET model, consistent between transient and small-signal simulations, has been developed for surface-potential-based MOSFET compact models. The new model is valid for all regions of operation and is compatible with, and at low frequencies recovers, the quasi-static (QS) description of the MOSFET. The model is implemented in two widely used circuit simulators and tested for speed and convergence. It is verified by comparison with technology computer aided design (TCAD) simulations and experimental data, and by application of a recently developed benchmark test for NQS MOSFET models. In addition, a new and simple technique to characterize NQS and gate resistance, Rgate, MOS model parameters from measured data has been presented. In the process of experimental model verification, the effects of bulk resistance on MOSFET characteristics is investigated both theoretically and experimentally to separate it from the NQS effects. / Dissertation/Thesis / Ph.D. Electrical Engineering 2012

O presente trabalho descreve o projeto de modelos neurais pulsados em tecnologia CMOS. Foram projetados dois modelos: um neurônio baseado em condutâncias e um neurônio do tipo integra e dispara. O primeiro gera impulsos elétricos similares aos potenciais de ação gerados pelo neurônio biológico. Mediante simulação, foram observadas as seguintes características: disparo do impulso quando se atinge a tensão de limiar, hiperpolarização após o potencial de ação, retorno passivo à tensão de repouso, presença de período refratário e relação sigmoide entre a frequência de disparo e a intensidade do estímulo. Da mesma maneira, foi reproduzida a curva mínima duração x amplitude de estímulo típico dos neurônios biológicos. O segundo realiza a codificação de uma grandeza analógica na fase relativa dos impulsos elétricos gerados. Os impulsos gerados pelo circuito estão afastados em relação a um sinal periódico, em um intervalo que apresenta uma dependência logarítmica de uma corrente de entrada. John Hopfield propus esse tipo de codificação para explicar o reconhecimento de padrões com independência de escala, realizado pelo cérebro humano. No decorrer da pesquisa, foi necessário desenvolver algumas expressões analíticas para o projeto de circuitos de baixa frequência em CMOS, não encontradas na literatura estudada. As expressões estão baseadas na equação da corrente do transistor MOS proposta no modelo conhecido como Advanced Compact Mosfet (ACM). O projeto, implementação e testes de um transcondutor linearizado, e os resultados das simulações dos modelos neurais projetados, demonstram a validade das expressões desenvolvidas. / This work describes the design of pulsed neural models in CMOS technology. Two models were designed: a conductance based neuron and an integrate and fire neuron. The first generates electrical impulses similar to action potentials generated by the biological neuron. Through simulation, the following characteristics were observed: pulse trigger after reaching threshold voltage, hyperpolarization after the action potential, passive return to resting potential, presence of refractory period and sigmoid relationship between the firing rate and the stimulus intensity. Likewise, the curve minimal duration vs stimulus amplitude typical of biological neurons was reproduced. The second one performs the encoding of an analog input in the relative phase of electrical impulses. The impulses generated by the circuit are delayed with respect to a reference periodic signal, in a range that has a logarithmic dependence on an input current. John Hopfield proposed this type of encoding to explain the scale independent pattern recognition performed by the human brain. During the research, it was necessary to develop some analytical expressions for the design of low-frequency circuits in CMOS, not found in the literature studied. The expressions are based on the Advanced Compact MOSFET (ACM) model. The design, implementations and testing of a linearized transconductor, and the simulations results of the neural models designed, demonstrate the validity of the expressions developed.

O presente trabalho descreve o projeto de modelos neurais pulsados em tecnologia CMOS. Foram projetados dois modelos: um neurônio baseado em condutâncias e um neurônio do tipo integra e dispara. O primeiro gera impulsos elétricos similares aos potenciais de ação gerados pelo neurônio biológico. Mediante simulação, foram observadas as seguintes características: disparo do impulso quando se atinge a tensão de limiar, hiperpolarização após o potencial de ação, retorno passivo à tensão de repouso, presença de período refratário e relação sigmoide entre a frequência de disparo e a intensidade do estímulo. Da mesma maneira, foi reproduzida a curva mínima duração x amplitude de estímulo típico dos neurônios biológicos. O segundo realiza a codificação de uma grandeza analógica na fase relativa dos impulsos elétricos gerados. Os impulsos gerados pelo circuito estão afastados em relação a um sinal periódico, em um intervalo que apresenta uma dependência logarítmica de uma corrente de entrada. John Hopfield propus esse tipo de codificação para explicar o reconhecimento de padrões com independência de escala, realizado pelo cérebro humano. No decorrer da pesquisa, foi necessário desenvolver algumas expressões analíticas para o projeto de circuitos de baixa frequência em CMOS, não encontradas na literatura estudada. As expressões estão baseadas na equação da corrente do transistor MOS proposta no modelo conhecido como Advanced Compact Mosfet (ACM). O projeto, implementação e testes de um transcondutor linearizado, e os resultados das simulações dos modelos neurais projetados, demonstram a validade das expressões desenvolvidas. / This work describes the design of pulsed neural models in CMOS technology. Two models were designed: a conductance based neuron and an integrate and fire neuron. The first generates electrical impulses similar to action potentials generated by the biological neuron. Through simulation, the following characteristics were observed: pulse trigger after reaching threshold voltage, hyperpolarization after the action potential, passive return to resting potential, presence of refractory period and sigmoid relationship between the firing rate and the stimulus intensity. Likewise, the curve minimal duration vs stimulus amplitude typical of biological neurons was reproduced. The second one performs the encoding of an analog input in the relative phase of electrical impulses. The impulses generated by the circuit are delayed with respect to a reference periodic signal, in a range that has a logarithmic dependence on an input current. John Hopfield proposed this type of encoding to explain the scale independent pattern recognition performed by the human brain. During the research, it was necessary to develop some analytical expressions for the design of low-frequency circuits in CMOS, not found in the literature studied. The expressions are based on the Advanced Compact MOSFET (ACM) model. The design, implementations and testing of a linearized transconductor, and the simulations results of the neural models designed, demonstrate the validity of the expressions developed.

In this work, a design platform for the modeling, simulation and optimization of fluidic components and their interactions in larger systems is developed. A hydrogel-based stimulus-sensitive microvalve is the core element of the microfluidic toolbox. Essential material properties as swelling-stimuli functions and the cooperative diffusion are extracted from measurements. The results provide necessary input data for finite element simulations in order to extract characteristic properties of the mechanical and fluid domains. Finally, the behavior of the microvalve and other fluidic library elements is implemented in Matlab Simscape for component and system simulations. Case studies and design optimization can be realized in a very short time with high accuracy. The toolbox is suitable for research and development and as software for academic education. The library elements are evaluated for a chemofluidic NAND gate, a chemofluidic decoder and a chemofluidic oscillator.:1 Introduction to Microfluidic Systems 1.1 Chemofluidic Enables Scalable and Logical Microfluidics 1.2 Focus of this Work 2 Fundamentals for Hydrogel-based Lab-on-Chip Systems 2.1 Basic Hydrogel Material Behavior 2.1.1 Basic Swelling Behavior 2.1.2 General Properties of Hydrogels 2.2 Overview of the used Microtechnology 2.2.1 Synthesis of P(NIPAAm-co-SA) 2.2.2 Microfabrication of a Microfluidic Chip 2.3 Introduction to Modeling and Simulation Techniques 2.3.1 Computer-aided Design Methodologies 2.3.2 Model Abstraction Levels for Computer-Aided Design 2.3.3 Modeling Techniques for Microvalves in a Fluidic System 3 Analytical Descriptions of Swelling 3.1 Quasi-Static Description 3.1.1 Physical Static Chemo-Thermal Description 3.1.2 Finite Element Routine for Static Thermo-Elastic Expansion 3.1.3 Static System Level Design for Hydrogel Swelling 3.2 Transient Description 3.2.1 Physical Dynamic Chemo-Thermal Description 3.2.2 Finite Element Routine for Dynamic Thermo-Elastic Expansion 3.2.3 Transient System Level Design for Hydrogel Swelling 3.3 Swelling Hysteresis Effect 3.3.1 Quasi-static Hysteresis 3.3.2 Transient Hysteresis 4 Characterization of Hydrogel 4.1 Data Acquisition through Automated Measurements 4.1.1 Measuring the Swelling of Hydrogels 4.1.2 Contactless Measurement Concept to Determine the Core Stiffness of Hydrogels 4.2 Data Evaluation with Image Recognition 4.3 Data Fitting and Model Adaption 4.3.1 Quasi-static Response 4.3.2 Transient Response 4.3.3 Hysteresis Response 5 Modeling Swelling in Finite Elements 5.1 Validity of the Model and Simulation Approach 5.2 Thermo-Mechanical Model of the Hydrogel Expansion Behavior 5.2.1 Change of the Length by Thermal Expansion 5.2.2 Stress-Strain Relationship for Hydrogels 5.2.3 Thermal Volume Expansion and Parameter Adaptation 5.2.4 Heat Transfer Coefficient 5.3 Volume Phase-Transition of a Hydrogel implemented in ANSYS 5.4 Computational Fluid Dynamics 5.4.1 Analytic Mesh Morphing 5.4.2 One-way Fluid Structure Interaction Modeling 5.4.3 Towards a Two-way Fluid Structure Interaction Model in CFX 6 Lumped Modeling 6.1 The Chemical Volume Phase-transition Transistor Model 6.1.1 Static Hysteresis 6.1.2 Equilibrium Swelling Length – Quasi-static Behavior 6.1.3 Kinematic Swelling Length - Transient Behavior 6.1.4 Stiffness and Maximum Closing Pressure 6.1.5 Calculation of the Fluidic Conductance 6.1.6 Modeling of the Fluid Flow through the Valve 6.2 Circuit Descriptions Analogy for Microfluidic Applications 6.2.1 Advantages and Limitations of Combined Simulink-Simscape Models 6.2.2 Requirements for Microfluidic Circuits 6.2.3 Graphical User Interfaces and Library Element Management 6.3 Modeling Techniques for the Chemical Volume Phase-transition Transistor (CVPT) 6.3.1 Network Description of CVPT 6.3.2 Signal Flow Description of CVPT 6.3.3 Mixed Signal Flow and Network Model for CVPT 7 Micro-Fluidic Toolbox 7.1 Microfluidic Components 7.1.1 Fluid Sources and Stimuli Sources 7.1.2 Fluidic Resistor with Bidirectional Stimulus Transport 7.1.3 Junctions 7.1.4 Chemical Volume Phase-transition Transistor 7.2 Microfluidic Matlab Toolbox 7.3 Modeling Chemofluidic Logic Circuits 7.3.1 Chemofluidic NAND Gate 7.3.2 Chemofluidic Decoder Application 7.3.3 Chemo-Fluidic Oscillator 7.4 Layout Synthesis 8 Summary and Outlook Appendix A 2D Thermo-Mechanical Solid Element for the Finite Element Method B Thermal Expansion Equation for ANSYS C Linear Regression of the Thermal Expansion Equation for ANSYS D Comparing different Mechanical Strain Definitions E Supporting Documents E.1 Analytic Static Swelling E.2 FEM - Matrix Method E.3 8 Node Finite Element Routine E.4 FEM - Script to create the CTEX table data E.5 Comparison of Solid Mechanics / In dieser Arbeit wird eine Entwurfsplattform für die Modellierung, Simulation und Optimierung von fluidischen Komponenten und deren Wechselwirkungen in größeren Systemen entwickelt. Ein Mikroventil auf der Basis von stimuli-sensitiven Hydrogelen ist das Kernelement des Entwurfstools. Wesentliche Materialeigenschaften wie das Quellverhalten und der kooperative Diffusionskoeffizient werden zu Beginn mit Messungen ermittelt. Mit Finite-Elemente-Simulationen werden aus diesen Daten charakteristische Kennwerte für das mechanische und fluidische Verhalten bestimmt. Sie bilden die Basis für komplexe Systemmodelle in Matlab Simscape, welche das Mikroventil und weitere fluidische Grundelemente in ihrem Zusammenwirken beschreiben. Verschiedene Konzepte können in kurzer Zeit und mit hoher Genauigkeit analysiert, optimiert und verglichen werden. Die Toolbox eignet sich für die Forschung und Entwicklung sowie als Software für die akademische Ausbildung. Sie wurde für den Entwurf eines chemofluidischen NAND-Gatters, für einen chemofluidischen Decoder und für einen chemofluidischen Oszillator eingesetzt.:1 Introduction to Microfluidic Systems 1.1 Chemofluidic Enables Scalable and Logical Microfluidics 1.2 Focus of this Work 2 Fundamentals for Hydrogel-based Lab-on-Chip Systems 2.1 Basic Hydrogel Material Behavior 2.1.1 Basic Swelling Behavior 2.1.2 General Properties of Hydrogels 2.2 Overview of the used Microtechnology 2.2.1 Synthesis of P(NIPAAm-co-SA) 2.2.2 Microfabrication of a Microfluidic Chip 2.3 Introduction to Modeling and Simulation Techniques 2.3.1 Computer-aided Design Methodologies 2.3.2 Model Abstraction Levels for Computer-Aided Design 2.3.3 Modeling Techniques for Microvalves in a Fluidic System 3 Analytical Descriptions of Swelling 3.1 Quasi-Static Description 3.1.1 Physical Static Chemo-Thermal Description 3.1.2 Finite Element Routine for Static Thermo-Elastic Expansion 3.1.3 Static System Level Design for Hydrogel Swelling 3.2 Transient Description 3.2.1 Physical Dynamic Chemo-Thermal Description 3.2.2 Finite Element Routine for Dynamic Thermo-Elastic Expansion 3.2.3 Transient System Level Design for Hydrogel Swelling 3.3 Swelling Hysteresis Effect 3.3.1 Quasi-static Hysteresis 3.3.2 Transient Hysteresis 4 Characterization of Hydrogel 4.1 Data Acquisition through Automated Measurements 4.1.1 Measuring the Swelling of Hydrogels 4.1.2 Contactless Measurement Concept to Determine the Core Stiffness of Hydrogels 4.2 Data Evaluation with Image Recognition 4.3 Data Fitting and Model Adaption 4.3.1 Quasi-static Response 4.3.2 Transient Response 4.3.3 Hysteresis Response 5 Modeling Swelling in Finite Elements 5.1 Validity of the Model and Simulation Approach 5.2 Thermo-Mechanical Model of the Hydrogel Expansion Behavior 5.2.1 Change of the Length by Thermal Expansion 5.2.2 Stress-Strain Relationship for Hydrogels 5.2.3 Thermal Volume Expansion and Parameter Adaptation 5.2.4 Heat Transfer Coefficient 5.3 Volume Phase-Transition of a Hydrogel implemented in ANSYS 5.4 Computational Fluid Dynamics 5.4.1 Analytic Mesh Morphing 5.4.2 One-way Fluid Structure Interaction Modeling 5.4.3 Towards a Two-way Fluid Structure Interaction Model in CFX 6 Lumped Modeling 6.1 The Chemical Volume Phase-transition Transistor Model 6.1.1 Static Hysteresis 6.1.2 Equilibrium Swelling Length – Quasi-static Behavior 6.1.3 Kinematic Swelling Length - Transient Behavior 6.1.4 Stiffness and Maximum Closing Pressure 6.1.5 Calculation of the Fluidic Conductance 6.1.6 Modeling of the Fluid Flow through the Valve 6.2 Circuit Descriptions Analogy for Microfluidic Applications 6.2.1 Advantages and Limitations of Combined Simulink-Simscape Models 6.2.2 Requirements for Microfluidic Circuits 6.2.3 Graphical User Interfaces and Library Element Management 6.3 Modeling Techniques for the Chemical Volume Phase-transition Transistor (CVPT) 6.3.1 Network Description of CVPT 6.3.2 Signal Flow Description of CVPT 6.3.3 Mixed Signal Flow and Network Model for CVPT 7 Micro-Fluidic Toolbox 7.1 Microfluidic Components 7.1.1 Fluid Sources and Stimuli Sources 7.1.2 Fluidic Resistor with Bidirectional Stimulus Transport 7.1.3 Junctions 7.1.4 Chemical Volume Phase-transition Transistor 7.2 Microfluidic Matlab Toolbox 7.3 Modeling Chemofluidic Logic Circuits 7.3.1 Chemofluidic NAND Gate 7.3.2 Chemofluidic Decoder Application 7.3.3 Chemo-Fluidic Oscillator 7.4 Layout Synthesis 8 Summary and Outlook Appendix A 2D Thermo-Mechanical Solid Element for the Finite Element Method B Thermal Expansion Equation for ANSYS C Linear Regression of the Thermal Expansion Equation for ANSYS D Comparing different Mechanical Strain Definitions E Supporting Documents E.1 Analytic Static Swelling E.2 FEM - Matrix Method E.3 8 Node Finite Element Routine E.4 FEM - Script to create the CTEX table data E.5 Comparison of Solid Mechanics

The continuous miniaturization of electronic systems using the three-dimensional (3D) integration technique has brought in new challenges for the computer-aided design and modeling of 3D integrated circuits (ICs) and systems. The major challenges for the modeling and analysis of 3D integrated systems mainly stem from four aspects: (a) the interaction between the electrical and thermal domains in an integrated system, (b) the increasing modeling complexity arising from 3D systems requires the development of multiscale techniques for the modeling and analysis of DC voltage drop, thermal gradients, and electromagnetic behaviors, (c) efficient modeling of microfluidic cooling, and (d) the demand of performing fast thermal simulation with varying design parameters. Addressing these challenges for the electrical/thermal modeling and analysis of 3D systems necessitates the development of novel numerical modeling methods. This dissertation mainly focuses on developing efficient electrical and thermal numerical modeling and co-simulation methods for 3D integrated systems. The developed numerical methods can be classified into three categories. The first category aims to investigate the interaction between electrical and thermal characteristics for power delivery networks (PDNs) in steady state and the thermal effect on characteristics of through-silicon via (TSV) arrays at high frequencies. The steady-state electrical-thermal interaction for PDNs is addressed by developing a voltage drop-thermal co-simulation method while the thermal effect on TSV characteristics is studied by proposing a thermal-electrical analysis approach for TSV arrays. The second category of numerical methods focuses on developing multiscale modeling approaches for the voltage drop and thermal analysis. A multiscale modeling method based on the finite-element non-conformal domain decomposition technique has been developed for the voltage drop and thermal analysis of 3D systems. The proposed method allows the modeling of a 3D multiscale system using independent mesh grids in sub-domains. As a result, the system unknowns can be greatly reduced. In addition, to improve the simulation efficiency, the cascadic multigrid solving approach has been adopted for the voltage drop-thermal co-simulation with a large number of unknowns. The focus of the last category is to develop fast thermal simulation methods using compact models and model order reduction (MOR). To overcome the computational cost using the computational fluid dynamics simulation, a finite-volume compact thermal model has been developed for the microchannel-based fluidic cooling. This compact thermal model enables the fast thermal simulation of 3D ICs with a large number of microchannels for early-stage design. In addition, a system-level thermal modeling method using domain decomposition and model order reduction is developed for both the steady-state and transient thermal analysis. The proposed approach can efficiently support thermal modeling with varying design parameters without using parameterized MOR techniques.

Une des principales solutions technologiques liées à la réduction d’échelle de la technologie CMOS est aujourd’hui clairement orientée vers les transistors MOSFET faiblement dopés à multiples grilles. Ceux-ci proposent une meilleure immunité contre les effets canaux courts comparés aux transistors MOSFET bulk planaires (cf. ITRS 2011). Parmi les MOSFETs à multiples grilles, le transistor FinFET SOI est un candidat intéressant de par la similarité de son processus de fabrication avec la technologie des transistors planaires. En parallèle, il existe une réelle attente de la part des concepteurs et des fonderies à disposer de modèles compacts efficaces numériquement, précis et proches de la physique, insérés dans les « design tools » permettant alors d’étudier et d’élaborer des circuits ambitieux en technologie FinFET. Cette thèse porte sur l’élaboration d’un modèle compact orienté conception du transistor FinFET valide aux dimensions nanométriques. Ce modèle prend en compte les effets canaux courts, la modulation de longueur de canal, la dégradation de la mobilité, leseffets de mécanique quantique et les transcapacités. Une validation de ce modèle est réalisée par des comparaisons avec des simulations TCAD 3D. Le modèle compact est implémenté en langage Verilog-A afin de simuler des circuits innovants à base de transistors FinFET. Une modélisation niveau-porte est développée pour la simulation de circuits numériques complexes. Cette thèse présente également un modèle compact générique de transistors MOSFET SOI canaux long faiblement dopés à multiple grilles. La dépendance à la température est prise en compte. Selon un concept de transformation géométrique, notre modèle compact du transistor MOSFET double grille planaire est étendu pour s’appliquer à tout autre type de transistor MOSFET à multiple grille (MuGFET). Une validation expérimentale du modèle MuGFET sur un transistor triple grille est proposée. Cette thèse apporte enfin des solutions pour la modélisation des transistors MOSFET double grille sans jonction. / One of the main technological solutions related to downscaling of CMOS technology is now clearly oriented to lightly doped multigate MOSFETs. They offer better immunity against short channel effects compared to planar bulk MOSFETs (see ITRS 2011). Among the multigate MOSFETs, the SOI FinFET transistor is an interesting candidate because of the similarity of its manufacturing process with the planar transistor technology. In parallel, there is a real expectation on the part of designers and foundries to have compact models numerically efficient, accurate and close to the physics, and then inserted in to the design tools in order to study and develop ambitious circuits in FinFET technology. This thesis focuses on the development of a design-oriented compact model of FinFET transistor valid to nanoscale dimensions. This model takes into account the short channel effects, the channel length modulation, the mobility degradation, the quantum mechanic effects and the transcapacitances. A validation of this model is carried out by comparisons with 3DTCAD simulations. The compact model is implemented in Verilog-A to simulate innovative FinFET-based circuits. A gate-level modeling is developed for the simulation of complex digital circuits. This thesis also presents a generic compact modeling of multigate SOI MOSFETs with lightly doped channels and temperature dependent. According to a concept of geometric transformation, our compact model of the planar double-gate MOSFET is extended to be applied to any other type of multigate MOSFETs (MuGFET). An experimental validation of the MuGFET compact model with a triple gate transistor is proposed. This thesis finally brings solutions for the modeling of junction less double-gate MOSFET.

Le développement de la technologie CMOS a déclenché une révolution dans la production IC. Chaque nouvelle génération technologique, par la mise à l’échelle des dimensions, a entraîné une accélération de son fonctionnement et une réduction de sa consommation. Cependant, la miniaturisation sera contrainte par les limites physiques fondamentales régissant la commutation des dispositifs CMOS dès lors que la technologie atteint des dimensions inférieures à 10 nm. Les chercheurs veulent trouver d'autres moyens de dépasser ces limites physiques. La spintronique est l’un des concepts les plus prometteurs pour de nouvelles applications de circuits intégrés sans courant de charge. La STT-MRAM est l’une des technologies de mémoires fondée sur la spintronique qui entre avec succès en phase de production de masse. Les opérateurs logiques à base de spin, associés aux métiers, doivent être maintenant étudiés. Notre recherche porte sur le domaine des transistors à effet de champ de spin (spin-FET), l'un des dispositifs logiques fondamentaux à base de spin. Le mécanisme principal pour réaliser un spin-FET consiste à contrôler le spin des électrons, ce qui permet d'atteindre l'objectif de réduction de puissance. De plus, en tant que dispositifs à spin, les spin-FET peuvent facilement être combinés à des éléments de stockage magnétique, tels que la jonction tunnel magnétique (MTJ), pour développer une architecture à «logique non volatile» offrant des performances de hautes vitesses et de faible consommation. La thèse présentée ici consiste à développer un modèle compact de spin-FET et à explorer les possibilités de son application pour la conception logique et la simulation logique non volatile. Tout d'abord, nous avons proposé un modèle à géométrie non locale pour spin-FET afin de décrire les comportements des électrons, tels que l'injection et la détection de spin, le décalage de phase d'angle de spin induit par l'interaction spin-orbite. Nous avons programmé un modèle spin-FET non local à l'aide du langage Verilog-A et l'avons validé en comparant la simulation aux résultats expérimentaux. Afin de développer un modèle électrique pour la conception et la simulation de circuits, nous avons proposé un modèle de géométrie local pour spin-FET basé sur le modèle non-local spin-FET. Le modèle de spin-FET local étudié peut être utilisé pour la conception logique et la simulation transitoire à l'aide d'outil de conception de circuit. Deuxièmement, nous avons proposé un modèle spin-FET à plusieurs grilles en améliorant le modèle susmentionné. Afin d'améliorer les performances du spin-FET, nous avons mis en cascade le canal en utilisant une structure d'injection / détection de spin partagée. En concevant différentes longueurs de canal, le spin-FET à plusieurs grilles peut agir comme différentes portes logiques. Les performances de ces portes logiques sont analysées par rapport à la logique CMOS conventionnelle. En utilisant les portes logiques multi-grille à spin-FET, nous avons conçu et simulé un certain nombre de blocs logiques booléens. La fonctionnalité des blocs logiques est démontrée par le résultat de simulations transitoires à l'aide du modèle spin-FET à plusieurs grilles. Enfin, en combinant le modèle spin-FET et le modèle multi-grille spin-FET avec le modèle d'élément de stockage MTJ, les portes à «logique non volatile» sont proposées. Comme le seul signal de pur spin peut atteindre le côté détection du spin-FET, la MTJ reçoit un courant de pur spin pour le transfert de spin. Dans ce cas, la commutation de la MTJ peut être plus efficace par rapport à la structure conventionnelle MTJ / CMOS. La comparaison des performances entre la structure hybride MTJ / spin-FET et la structure hybride MTJ / CMOS est démontrée par un calcul de retard et de courant critique qui est dérivé de l'équation de Landau-Lifshitz-Gilbert (LLG). La simulation transitoire valide le fonctionnement de la logique non volatile basée sur MTJ / spin-FET. / The development of Complementary Metal Oxide Semiconductor (CMOS) technology drives the revolution of the integrate circuits (IC) production. Each new CMOS technology generation is aimed at the fast and low-power operation which mostly benefits from the scaling with its dimensions. However, the scaling will be influenced by some fundamental physical limits of device switching since the CMOS technology steps into sub-10 nm generation. Researchers want to find other ways for addressing the physical limitation problem. Spintronics is one of the most promising fields for the concept of non-charge-based new IC applications. The spin-transfer torque magnetic random access memory (STT-MRAM) is one of the successful spintronics-based memory devices which is coming into the volume production stage. The related spin-based logic devices still need to be investigated. Our research is on the field of the spin field effect transistors (spin-FET), one of the fundamental spin-based logic devices. The main mechanism for realizing a spin-FET is controlling the spin of the electrons which can achieve the objective of power reduction. Moreover, as spin-based devices, the spin-FET can easily combine with spin-based storage elements such as magnetic tunnel junction (MTJ) to construct the “non-volatile logic” architecture with high-speed and low-power performance. Our focus in this thesis is to develop the compact model for spin-FET and to explore its application on logic design and non-volatile logic simulation. Firstly, we proposed the non-local geometry model for spin-FET to describe the behaviors of the electrons such as spin injection and detection, the spin angle phase shift induced by spin-orbit interaction. We programmed the non-local spin-FET model using Verilog-A language and validated it by comparing the simulation with the experimental result. In order to develop an electrical model for circuit design and simulation, we proposed the local geometry model for spin-FET based on the non-local spin-FET model. The investigated local spin-FET model can be used for logic design and transient simulation on the circuit design tool. Secondly, we proposed the multi-gate spin-FET model by improving the aforementioned model. In order to enhance the performance of the spin-FET, we cascaded the channel using a shared spin injection/detection structure. By designing different channel length, the multi-gate spin-FET can act as different logic gates. The performance of these logic gates is analyzed comparing with the conventional CMOS logic. Using the multi-gate spin-FET-based logic gates, we designed and simulated a number of the Boolean logic block. The logic block is demonstrated by the transient simulation result using the multi-gate spin-FET model. Finally, combing the spin-FET model and multi-gate spin-FET model with the storage element MTJ model, the “non-volatile logic” gates are proposed. Since the only pure spin signal can reach to the detection side of the spin-FET, the MTJ receives pure spin current for the spin transfer. In this case, the switching of the MTJ can be more effective compared with the conventional MTJ/CMOS structure. The performance comparison between hybrid MTJ/spin-FET structure and hybrid MTJ/CMOS structure are demonstrated by delay and critical current calculation which are derived from Landau-Lifshitz-Gilbert (LLG) equation. The transient simulation verifies the function of the MTJ/spin-FET based non-volatile logic.