This thesis reports the calibration, imaging and analysis of one epoch of VLBI observations of the v (italics) = J (italics) = 1-0 transition of SiO towards VY CMa. Full polarisation information was recorded, allowing high resolution synthesis maps of each of the four Stokes parameters to be produced. A total of 81 maser components were extracted from the total intensity map, each approximately 1 mas in size. The emission spans approximately 100 x 80 mas in right ascension and declination and is concentrated to the east. The maser component positions were fitted to a ring of radius ~ 3.2R₊ (italics), or 7.2 x 1O¹⁴ cm for a stellar distance of 1.5 kpc. If the stellar position is assumed to be the centre of this ring then almost all of the maser components fall within the inner dust shell radius, which is at ~ 5R (italics)ϰ All of the maser components fall between 1.5R (italics)ϰ and 6R (italics)ϰ. A velocity gradient with position angle was observed in the sparsely filled western region of the maser ring. If interpreted as evidence of shell rotation, this gradient implies a rotational velocity of v (italics) rot (subscirpt) sin i (italics) = 18 km.s⁻¹. The fractional circular and linear polarisations of the maser spots were derived from the Stokes parameter maps. The mean fractional circular polarisation of the masers components was ~ 2 percent and the median fractional linear polarisation was ~ 6 percent, with many spots displaying over ~ 30 percent linear polarisation. The mean circular polarisation implies a magnetic field of ~ 4 G in the SiO maser region if the polarisation is due to Zeeman splitting. Two maser components display a rotation of linear polarisation position angle with velocity, possibly implying a connection between the magnetic field and the velocity field variations in the region of these components.

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VLSI testing poses a number of problems which includes the selection of test techniques, the determination of acceptable fault coverage levels, and test vector generation. Available device test techniques are examined and compared. Design rules should be employed to assure the design is testable. Logic simulation systems and available test utilities are compared. The various methods of test vector generation are also examined. The selection criteria for test techniques are identified. A table of proposed design rules is included. Testability measurement utilities can be used to statistically predict the test generation effort. Field reject rates and fault coverage are statistically related. Acceptable field reject rates can be achieved with less than full test vector fault coverage. The methods and techniques which are examined form the basis of the recommended integrated test plan. The methods of automatic test vector generation are relatively primitive but are improving.

A set S of vertices in a graph G=(V,E) is a dominating set if every vertex in V\S is adjacent to at least one vertex in S, and the minimum cardinality of a dominating set of G is the domination number of G. A vertex v in a dominating set S is said to be very cost effective if it is adjacent to more vertices in V\S than to vertices in S. A dominating set S is very cost effective if every vertex in S is very cost effective. The minimum cardinality of a very cost effective dominating set of G is the very cost effective domination number of G. We first give necessary conditions for a graph to have equal domination and very cost effective domination numbers. Then we determine an upper bound on the very cost effective domination number for trees in terms of their domination number, and characterize the trees which attain this bound. lastly, we show that no such bound exists for graphs in general, even when restricted to bipartite graphs.

Low resistance gate level interconnects can free the design of VLSI circuits from the R-C time constant limitations currently imposed by poly-silicon based technology. The hotwall low pressure chemical vapor deposition of molybdenum and tungsten silicide from their commercially available hexacarbonyls and silane is presented as a deposition method producing IC-compatible gate electrodes of reduced resistivity. Good hotwall deposition uniformity is demonstrated at low temperatures (200 to 300 C). The as-deposited films are amorphous by x-ray diffraction and can be crystallized in subsequent anneal steps with anneal induced film shrinkage of less than 12 percent. Surface oxide formation is possible during this anneal cycle. Auger spectroscopy and Rutherford backscattering results indicate that silicon-rich films can be deposited, and that the concentrations of carbon and oxygen incorporated from the carbonyl source are a function of the deposition parameters. At higher deposition temperatures and larger source throughput the impurity incorporation is markedly reduced. Good film adhesion and excellent step coverage are observed. Electrical measurements show that the film resistivities after anneal are comparable to those of sputtered or evaporated silicide films. Bias-temperature capacitance-voltage measurements demonstrate that direct silicide gate electrodes have properties comparable to standard metal-oxide-silicon systems. The substitution of CVD silicides for standard MOS gate metals appears to be transparent in terms of transistor performance, except for work function effects on the threshold voltage. The large wafer throughput and good step coverage of hotwall low pressure silicide deposition thus promises to become a viable alternative to the poly-silicon technology currently in use.

The apoC-III proteoform containing two sialic acid residues (apoC-III2) has different in vitro effects on lipid metabolism compared with asialylated (apoC-III0) or the most abundant monosialylated (apoC-III1) proteoforms. Cross-sectional and longitudinal associations between plasma apoC-III proteoforms (by mass spectrometric immunoassay) and plasma lipids were tested in two randomized clinical trials: ACT NOW, a study of pioglitazone in subjects with impaired glucose tolerance (n = 531), and RACED (n = 296), a study of intensive glycemic control and atherosclerosis in type 2 diabetes patients. At baseline, higher relative apoC-(I)II2 and apoC-III2/apoC-III1 ratios were associated with lower triglycerides and total cholesterol in both cohorts, and with lower small dense LDL in the RACED. Longitudinally, changes in apoC-III2/apoC-III1 were inversely associated with changes in triglycerides in both cohorts, and with total and small dense LDL in the RACED. apoC-III2/apoC-III1 was also higher in patients treated with PPAR-gamma agonists and was associated with reduced cardiovascular events in the RACED control group. Ex vivo studies of apoC-III complexes with higher apoC-III2/apoC-III1 showed attenuated inhibition of VLDL uptake by HepG2 cells and LPL-mediated lipolysis, providing possible functional explanations for the inverse association between a higher apoC-III2/apoC-III1 and hypertriglyceridemia, proatherogenic plasma lipid profiles, and cardiovascular risk.

published_or_final_version / abstract / Electrical and Electronic Engineering / Master / Master of Philosophy

Very Long Instruction Word (VLIW) processors are wide-issue statically scheduled processors. Instruction scheduling for these processors is performed by the compiler and is therefore a critical factor for its operation. Some VLIWs are clustered, a design that improves scalability to higher issue widths while improving energy efficiency and frequency. Their design is based on physically partitioning the shared hardware resources (e.g., register file). Such designs further increase the challenges of instruction scheduling since the compiler has the additional tasks of deciding on the placement of the instructions to the corresponding clusters and orchestrating the data movements across clusters. In this thesis we propose instruction scheduling optimizations for energy-efficient VLIW processors. Some of the techniques aim at improving the existing state-of-theart scheduling techniques, while others aim at using compiler techniques for closing the gap between lightweight hardware designs and more complex ones. Each of the proposed techniques target individual features of energy efficient VLIW architectures. Our first technique, called Aligned Scheduling, makes use of a novel scheduling heuristic for hiding memory latencies in lightweight VLIW processors without hardware load-use interlocks (Stall-On-Miss). With Aligned Scheduling, a software-only technique, a SOM processor coupled with non-blocking caches can better cope with the cache latencies and it can perform closer to the heavyweight designs. Performance is improved by up to 20% across a range of benchmarks from the Mediabench II and SPEC CINT2000 benchmark suites. The rest of the techniques target a class of VLIW processors known as clustered VLIWs, that are more scalable and more energy efficient and operate at higher frequencies than their monolithic counterparts. The second scheme (LUCAS) is an improved scheduler for clustered VLIW processors that solves the problem of the existing state-of-the-art schedulers being very susceptible to the inter-cluster communication latency. The proposed unified clustering and scheduling technique is a hybrid scheme that performs instruction by instruction switching between the two state-of-the-art clustering heuristics, leading to better scheduling than either of them. It generates better performing code compared to the state-of-the-art for a wide range of inter-cluster latency values on the Mediabench II benchmarks. The third technique (called CAeSaR) is a scheduler for clustered VLIW architectures that minimizes inter-cluster communication by local caching and reuse of already received data. Unlike dynamically scheduled processors, where this can be supported by the register renaming hardware, in VLIWs it has to be done by the code generator. The proposed instruction scheduler unifies cluster assignment, instruction scheduling and communication minimization in a single unified algorithm, solving the phase ordering issues between all three parts. The proposed scheduler shows an improvement in execution time of up to 20.3% and 13.8% on average across a range of benchmarks from the Mediabench II and SPEC CINT2000 benchmark suites. The last technique, applies to heterogeneous clustered VLIWs that support dynamic voltage and frequency scaling (DVFS) independently per cluster. In these processors there are no hardware interlocks between clusters to honor the data dependencies. Instead, the scheduler has to be aware of the DVFS decisions to guarantee correct execution. Effectively controlling DVFS, to selectively decrease the frequency of clusters with slack in their schedule, can lead to significant energy savings. The proposed technique (called UCIFF) solves the phase ordering problem between frequency selection and scheduling that is present in existing algorithms. The results show that UCIFF produces better code than the state-of-the-art and very close to the optimal across the Mediabench II benchmarks. Overall, the proposed instruction scheduling techniques lead to either better efficiency on existing designs or allow simpler lightweight designs to be competitive against ones with more complex hardware.

This dissertation describes an innovative approach to the state justification portion of the sequential circuit automatic test pattern generation (ATPG) process. Given the absence of a stored fault an ATPG controller invokes some combinational circuit test generation procedure, such as the D-algorithm, to identify a circuit state (goal state) and input vectors that will sensitize a selected fault. The state justification phase then finds a transfer sequence to the goal from the present state. A forward fault propogation search can be successfully guided through state space from the present state but the forward justification search is less efficient and the failure rate is high. The backward function level search invokes inverse RTL level primitives and exploits easy movement of data vectors in structured VLSI circuits. Examples illustrated are in AHPL. This search is equally applicable to an RTL level subset of VHDL. Combinational logic units are treated as functions and the circuit states are partitioned into control states and data states. The search proceeds backwards over the control state space starting from the goal state node and data states are transformed according to the control flow. Vectorized data paths in VLSI circuits and search guiding heuristics which favor convenient inverse functions keep the number of search nodes low. Partial covers, conceptually similar to singular covers in D-algorithm, model the inverse functions of combinational logic units. The search successfully terminates when a child state node logically matches the present state and the present state values can satisfy all the constraints encountered along the search path.

New VLSI and VHSIC devices require increased performance from electronic packages. The major challenge that must be met in materials/process development for high complexity and high speed integrated circuits is the processing of even larger amounts of signals with low propagation delay. Hence, materials with low dielectric constant and low dissipation factor are being sought. In this investigation the dielectric properties of the most commonly used composite materials for printed circuit boards, Teflon-glass and Epoxy-glass, were measured in the frequency and temperature intervals of 100 HZ-1 GHZ and 25-260°C, respectively. From the measured results, it is concluded that Teflon-glass is more suitable for the board level packaging of high performance circuits due to its lower dielectric constant and low dissipation factor.