Reed-Solomon (RS) codes are non-binary, forward error-correcting codes. The RS code is flexible, in that a code can be shortened, extended, interleaved and concatenated. This flexibility has made the RS code an important design block in communication system design and today the RS code is used within a large number of applications from data storage systems to space telecommunications. Implementations of the coding and decoding strategies have until recently been limited to software due to their high complexity, however, with recent advances in IC fabrication technology it has become possible for RS codecs to be implemented in hardware. A hardware implementation has a smaller silicon requirement, and makes the technology a more applicable solution for real-time applications. However, the problem for a hardware RS codec design solution today is the acknowledged lack of codec design experts. The work outlined in this document addresses this problem through the use of Design Automation (DA). This thesis describes a solution that employs a non-proprietary, technology independent generic VHDL core. The core is a single, self-contained generic circuit description, written entirely in standard synthesizable VHDL and can therefore be used by any synthesis tool on any CAD system to produce a gate-level description for any available technology. The core developed implements a bit-serial RS codec, using a time domain algorithm for encoding, and a frequency domain algorithm for decoding. Only a limited number of code description parameters are required to be entered into the core to produce a completed design in seconds. The results presented in the thesis illustrate in detail that the VHDL core generates efficient circuit architecture in terms of silicon area which are within I% of hand-crafted designs. Comparison of synthesized results to hand crafted designs are presented for all circuit structures from the simplest multiplier up to entire encoders and decoders. Technology independence has been illustrated through the use of synthesis of the core to a traditional semi-custom gate array, LSI Logic LCA300k series, and to a popular Xilinx FPGA. The actual circuit topology, and therefore the route of the circuit critical paths, for the gate array implementation are almost identical to the handcrafted design., since the VHDL core was based on experience gained in creating those circuits. The only differences are attributable to minor differences in synthesis cell libraries that affect the circuit topology in a small way and of course the resulting maximum clock rate which wi11 always be technology-dependent. Obviously, for other architectures, for example FPGAs, the actual route of the critical paths will also be different, but the technology dependence of the critical path is beyond the scope of this thesis.

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by Li Wai Ting. / Thesis (M.Ph.)--Chinese University of Hong Kong, 1987. / Includes bibliographical references.

He, Xu. / Thesis (Ph.D.)--Chinese University of Hong Kong, 2013. / Includes bibliographical references (leaves [127]-135). / Electronic reproduction. Hong Kong : Chinese University of Hong Kong, [2012] System requirements: Adobe Acrobat Reader. Available via World Wide Web. / Abstracts also in Chinese.