<p>The design and implementation of a synthesizable model of the Serial Communication Interface and Synchronous Serial Interface, which constitutes the Port C of Motorola DSP56002 is presented in this report. They serves as a full duplex serial interface to other DSPs, processors, codecs, digital-to-analog and analog-to-digital converters and other transducers. The SCI block is able to handle a data rate of 5Mbps in Synchronous mode and 625Kbps in asynchronous mode for a 40MHz clock. It supports five word formats including a multidrop mode for multiprocessor systems. SSI provides a data rate of 10Mbps for the same 40 MHz clock. The design includes a programmable on-chip or external baud rate generator/interrupt timer for the SCI and a clock generator and frame Sync generator for the SSI.</p><p>The thesis focus on arriving at a full functional description of individual blocks included with Port C from the data sheets and product users manual. From this operational description a behavioural model was developed. The structure and implementation is based on the Motorola DSP56002 with additional support for a variable data-width. The model is written completely in behavioural VHDL with a top-down approach and the model was verified and validated.</p>

The design and implementation of a synthesizable model of the Serial Communication Interface and Synchronous Serial Interface, which constitutes the Port C of Motorola DSP56002 is presented in this report. They serves as a full duplex serial interface to other DSPs, processors, codecs, digital-to-analog and analog-to-digital converters and other transducers. The SCI block is able to handle a data rate of 5Mbps in Synchronous mode and 625Kbps in asynchronous mode for a 40MHz clock. It supports five word formats including a multidrop mode for multiprocessor systems. SSI provides a data rate of 10Mbps for the same 40 MHz clock. The design includes a programmable on-chip or external baud rate generator/interrupt timer for the SCI and a clock generator and frame Sync generator for the SSI. The thesis focus on arriving at a full functional description of individual blocks included with Port C from the data sheets and product users manual. From this operational description a behavioural model was developed. The structure and implementation is based on the Motorola DSP56002 with additional support for a variable data-width. The model is written completely in behavioural VHDL with a top-down approach and the model was verified and validated.

As technology scales down and CMOS circuits are powered by lower supply voltages, standby leakage current becomes significant. A behavioral level framework for the synthesis of data-paths with low leakage power is presented. There has been minimal work done on the behavioral synthesis of low leakage datapaths. We present a fast architectural simulator for leakage (FASL) to estimate the leakage power dissipated by a system described hierarchically in VHDL. FASL uses a leakage power model embedded into VHDL leafcells. These leafcells are characterized for leakage accurately using HSPICE. We present results which show that FASL measures leakage power significantly faster than HSPICE, with less than a 5% loss in accuracy, compared to HSPICE. We present a comprehensive framework for synthesizing low leakage power data-paths using a parameterized Multi-threshold CMOS (MTCMOS) component library. The component library has been characterized for leakage power and delay as a function of sleep transistor width. We propose four techniques for minimization of leakage power during behavioral synthesis: (1) leakage power management using MTCMOS modules; (2) an allocation and binding algorithm for low leakage based on clique partitioning; (3) selective binding to MTCMOS technology, allowing the designer to have control over the area overhead; and (4) a performance recovery technique based on multi-cycling and introduction of slack, to alleviate the loss in performance attributed to the introduction of MTCMOS modules in the data-path. Finally, we propose two iterative search based techniques, based on Tabu search, to synthesize low leakage data-paths. The first technique searches for low leakage scheduling options. The second technique simultaneously searches for a low leakage schedule and binding. It is shown that the latter technique of unified search is more robust. The quality of results generated bytabu-based technique are superior to those generated by simulated annealing (SA) search technique.