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  • About
  • The Global ETD Search service is a free service for researchers to find electronic theses and dissertations. This service is provided by the Networked Digital Library of Theses and Dissertations.
    Our metadata is collected from universities around the world. If you manage a university/consortium/country archive and want to be added, details can be found on the NDLTD website.
71

Fast transient LDO using digital detection. / Fast transient low-dropout using digital detection

January 2012 (has links)
電源管理集成電路被廣泛應用於便攜式電子應用。在同一芯片需要不同的電源電壓水平。由於芯片尺寸,工作速度和所需功耗的要求,低壓差穩壓器(LDO)在快遞瞬態響應,低噪聲,以及高精度的電子產品中具有廣泛的應用。 / LDO的負載瞬間變化取決於功率金氧半場效電晶體的大小、偏置電流和誤差放大器的增益。檢測輸出電壓,並使用大電容和電阻通過電容耦合,增加偏置電流是一個簡單的方法來改善負載瞬間變化。然而,電阻電容佔據較大的芯片面積。 / 權衡功耗和芯片尺寸,本論文中提出用數字檢測電路取代用於瞬態耦合的大電容和電阻。所提出的電路是讓功率金氧半場效電晶體的栅極電容電流增加充電或放電,以提高LDO的負載瞬間響應速度。產生這種電流通過檢測內部的變化,並產生一個電壓脈衝控制迴轉電流,然後通過使用一組數字電路去改變充電或放電的電量。 / 擬議的設計已在UMC0.18微米 CMOS制程技術實現。LDO的輸入電壓為0.9伏至1.3伏和穩壓0.7伏。最大輸出電流為50豪安。經過測量,負載瞬間變化得到改善。負載瞬間的響應時間可以從75微秒(傳統)減少到75納秒。 / Power-management IC is widely used in portable electronic applications. Different supply voltage levels are required in the same chip. Due to the size, speed and power requirements, low-dropout regulator (LDO) is generally adopted for applications which need fast transient response, low noise and high accuracy. / Transient response of a LDO is limited by the size of power MOSFET, biasing current and gain of error amplifier. Detecting the output voltage and using large RC components for capacitive coupling to increase the biasing current is a straightforward method to improve the transient response. However, this requires a large chip size for the RC components. / By considering power consumption and size, digital detection circuit is proposed to replace the large capacitors and resistors used for transient coupling. The proposed circuit is to increase the charging or discharging current to the gate of the power MOSFET to increase the transient speed of LDO. This current is generated by detecting the internal changes and generating a voltage pulse to control the slewing current by using a set of digital circuit. / The proposed design has been realized in UMC 0.18μm CMOS technology. The input voltage of the LDO is 0.9 to 1.3V and the regulated voltage is 0.7V. The maximum output current is 50mA. From the measurement, the transient response is improved. The response time due to load transient changes can be reduced from 75s (conventional) to 75ns. / Detailed summary in vernacular field only. / Detailed summary in vernacular field only. / Detailed summary in vernacular field only. / Detailed summary in vernacular field only. / Kwong, Ka Yee. / Thesis (M.Phil.)--Chinese University of Hong Kong, 2012. / Includes bibliographical references. / Abstracts also in Chinese. / Abstract / Acknowledgments / Table of Content / List of Figures / List of Tables / Chapter Chapter 1 --- LDO regulator research background / Introduction / Chapter Section 1.1 --- Generic LDO regulator structure / Chapter Section 1.2 --- Principle of LDO regulator operation / Chapter Section 1.3 --- Specifications / Chapter References / Chapter Chapter 2 --- Review of state-of-the-art transient-improvement techniques for LDO regulators / Introduction / Chapter Section 2.1 --- Slew rate improvement at power transistor gate / Chapter Section 2.2 --- Frequency compensation / Chapter Section 2.3 --- Short summary / References / Chapter Chapter 3 --- A proposed output-capacitorless LDO regulator with digital voltage spike detection / Chapter Introduction / Chapter Section 3.1 --- LDO regulator core structure / Chapter Section 3.2 --- Digital switches based LDO regulator / Chapter Section 3.3 --- LDO regulator with proposed digital voltage spike detection circuit / Chapter Section 3.4 --- Simulation result / Chapter Section 3.5 --- Short summary / References / Chapter Chapter 4 --- Measurement results / Introduction / Chapter Chapter 5 --- Conclusion and Future Work
72

Topologies and Modelings of Novel Bipolar Gate Driver Techniques for Next-Generation High Frequency Voltage Regulators

FU, Jizhen 30 July 2010 (has links)
As is predicted by Moore’s law, the transistors in microprocessors increase dramatically. In order to increase the power density of the microprocessors, the switching frequency of the Voltage Regulator (VR) is expected to increase to MHz level. However, the frequency dependent loss will increase proportionally. In order to meet requirements of the next-generation microprocessors, three new ideas are proposed in this thesis. The first contribution is a new bipolar Current Source Driver (CSD) for high frequency power MOSFET. The proposed CSD alleviates the gate current diversion problem of the existing CSDs by clamping the gate voltage to a flexible negative value during turn off transition. Therefore, the proposed driver turns off the MOSFET much faster. For buck converters with 12 V input at 1MHz switching frequency, the proposed driver improves the efficiency from 80.5% using the existing CSD to 82.5% at 1.2V/30A, and at 1.3V/30A output, from 82.5% to 83.9%. The second contribution is an accurate analytical loss model of a power MOSFET with a CSD. The current diversion problem that commonly exists in CSDs is investigated mathematically. The inductor value of the CSD is optimized to achieve minimum loss for the synchronous buck converter. The experimentally measured loss matches the calculated loss very well. The efficiency with the optimal CSD inductor is improved from 86.1% to 87.6% at 12V input, 1.3V/20A output in 1MHz switching frequency and from 82.4% to 84.0% at 1.3V/30A output. The third contribution is a new inductorless bipolar gate driver for control FET of buck converters. The most important advantage of the driver presented in this thesis is that it can turn off the power MOSFETs with a negative voltage, which will significantly reduce the turn off time and thus switching loss. In addition, the proposed bipolar gate driver has no inductor in the driver circuit; therefore it can be fully integrated into a chip. For buck converter with 5V input, 1.3V/25A load, in 2 MHz frequency, the proposed gate driver increases the efficiency from 75.8% to 77.8% and from 72.9% to 76.5% at 5V input, 1.3V/25A load, in 2.5 MHz switching frequency. / Thesis (Master, Electrical & Computer Engineering) -- Queen's University, 2010-07-30 14:06:04.003
73

Voltage scaling constraints for static CMOS logic and memory cirucits

Bhavnagarwala, Azeez Jenúddin 05 1900 (has links)
No description available.
74

Investigating the financial recovery of embedded generation in medium voltage distribution systems.

Moonsamy, Raventhran. 29 October 2014 (has links)
Embedded generation (EG) provides many benefits in terms of reduction of system technical losses and increased load carrying capacity. In this study the sustainable EG carrying capacity permutations in a medium voltage distribution system, will be determined. Using these results, the financial investment recovery potential of EG will be studied and the impact on the cost recovery by the Utility as a result of compensating the EG at the current system marginal price, will be analysed. The study was done to show what capitalisation can be done on a medium voltage distribution system, by the owners of EG plant receiving revenue from the Utility, at the system margin price with the anticipated inflationary increases. The study will also cover the effect on the revenue stream of the Utility as a result of voltage changes caused by the EGs to the loads being supplied. The electrical system used in the study consisted of a radial system with distributed load and generation. The distributed loads were modelled using the average load capacity supplied by the Utility in medium voltage system. The average volume of sales lost as a result of non-technical losses was included in the load model so that the overall accuracy of the revenue effect by EG on the Utility, could be increased. The amount of capitalisation that is achievable by the owners of the EG was tested against various practical permutation scenarios, including variation of location, system impedance (different X/R ratios), time of operation and changing load volume and type. The extent of successful penetration of EG into the distribution system was found to be between 20% and 60% of the load carrying capacity of the system. The simulated results revealed “bathtub curve” behaviour for the cost of energy losses and this reconciled with the theoretical analysis of other studies done in this area. Lower volume penetration of EG results in higher investment potential of up to ten million rand per MW with a 5% MARR per year. This is very low when compared to the levelised cost of the expensive renewable energy technologies that are currently available in the market. With higher penetration of EG on low impedance systems, the gross contribution of the Utility is negatively affected which would introduce instability in the SMP yearly increases. / M. Sc. Eng. University of KwaZulu-Natal, Durban 2013.
75

Development of an improved on-line voltage stability index using synchronized phasor measurement

Gong, Yanfeng. January 2005 (has links)
Thesis (Ph.D.) -- Mississippi State University. Department of Electrical and Computer Engineering. / Title from title screen. Includes bibliographical references.
76

Application of STATCOM for improved dynamic performance of wind farms in a power grid

Jayam Prabhakar, Aditya, January 2008 (has links) (PDF)
Thesis (M.S.)--Missouri University of Science and Technology, 2008. / Vita. The entire thesis text is included in file. Title from title screen of thesis/dissertation PDF file (viewed May 12, 2008) Includes bibliographical references (p. 64-66).
77

Flicker propagation in radial and interconnected power systems

Tennakoon, Sankika. January 2008 (has links)
Thesis (Ph.D.)--University of Wollongong, 2008. / Typescript. Includes bibliographical references: page 150-155.
78

Opportunities for in-line, transistorbased technologies on MV and LV power distribution networks

Meyer, Bernard 12 1900 (has links)
Thesis (MScEng)--University of Stellenbosch, 2000. / ENGLISH ABSTRACT: Once more opportunities exist for innovative technologies to be applied on MV and LV power distribution networks to meet the new challenges set by government through its National Electrification Programme (NEP) to electrify a further 2,5 million households of which a large majority are in low-density rural areas. Electronic means of voltage compensation of long MV and LV networks supplying these low-density rural areas are now possible in the form of electronic voltage regulators mounted on the secondary side of distribution transformers and service connection boxes along the LV feeders. Furthermore, it is now possible to provide remote rural agricultural customers with singlephase supplies supported by end-use technologies in the form of electronic phase converters that eliminate the need for three-phase supplies. This hybrid of supply- and end-use technologies together with Eskom's "self-build" policy has made the dream of Eskom grid power a reality. / AFRIKAANSE OPSOMMING: Nuwe geleenthede het na yore getree vir die toepassing van innoverende tegnologie op medium- en laagspannings netwerke in antwoord op die uitdagings gestel deur die regering in die vorm van die Nasionale Elektrifiseringsprogram (NEP). Die elektrifisering van 'n verdere 2,5 miljoen huishoudings waarvan die grootste gedeelte in yl bevolkte plattelandse gebiede is, word in vooruitsig gestel. Spanningskompensasie van lang laag- en mediumspannings netwerke word nou moontlik gemaak deur middel van elektroniese spanningsreguleerders, gemonteer aan die sekondere kant van distribusie transformators en in diensaansluitingskaste op laagspannings voerders. Verder is dit ook nou moontlik om afgelee landelike plase met enkelfase krag, gerugsteun deur eindverbruik tegnologie in die vorm van elektroniese fase omsetters, te voorsien. Die beskikbaarheid van hierdie tegnologie elimineer die vraag na drie-fase krag. Hierdie hibriede kombinasie van toevoer- en eindverbruik tegnologie in kohesie met die selfbou beleid van Eskom, maak dit moontlik dat 'n droom van Eskom voorsiende elektrisiteit, in 'n werklikheid omskep word.
79

Voltage control of medium to high power three-phase inverter supply systems

Jacobs, D. M. (Danver Maxwill) 12 1900 (has links)
Thesis (MScEng)--University of Stellenbosch, 2001. / ENGLISH ABSTRACT: In this thesis a new voltage control method is developed for a three-phase inverter supply system. The inverter supply system consist of a Permanent Magnet Generator, a three-phase rectifier, a three-phase inverter plus LC-filter and a three-phase transformer in series. This system supplies power to a network or to a stand-alone load. The main focus of this thesis is on the control aspects of the inverter and the LC-filter. Different voltage control systems are investigated and compared to each other. From these methods the proposed voltage control method is developed where only the output voltages are measured to establish good voltage control. All these voltage control methods are also simulated with a software package. The proposed voltage control method compares very well with other voltage control methods. The results that are obtained in the simulations are satisfactory. The proposed voltage control method is also implemented in an 8 kW laboratory scale model and, again, very good practical results are obtained. A TMS320F240 nsp controller is used to implement the proposed voltage control method. The controller compensates well for load steps, and these results compare well to an alternative voltage control method, which was also evaluated practically. / AFRIKAANSE OPSOMMING: In hierdie tesis IS 'n nuwe spanningsbeheermetode ontwikkel VIr 'n drie-fase wisselrigter kragtoevoerstelsel. Die wisselrigter kragtoevoerstelsel bestaan uit 'n Permanent Magneet Generator, 'n drie-fase gelykrigter, 'n drie-fase wisselrigter plus Le-filter, en 'n drie-fase transformator in serie. Hierdie stelsel voorsien krag aan 'n netwerk sowel as aan 'n alleenstaande las. Die hooffokus van hierdie tesis is op die beheeraspekte van die wisselrigter en Le-filter. Verskillende spanningsbeheermetodes is deeglik ondersoek en vergelyk met mekaar. Uit hierdie metodes is dan die voorgestelde beheermetode ontwikkel waar slegs die uittreespanning gemeet word om goeie spanningsbeheer te kan doen. Al hierdie spanningsbeheermetodes is dan gesimuleer met 'n sagteware pakket. Die voorgestelde spanningsbeheermetode vergelyk baie goed met die ander spanningsbeheermetodes. Die resultate verky in die simulasies is ook baie bevredigend. Die voorgestelde beheermetode is ook geïmplementeer op 'n 8 kW laboratorium skaalmodel en weereens is baie goeie praktiese resultate verky. 'n TMS320F240 DSP-beheerder is gebruik om die voorgestelde beheermetode mee te implementeer. Die beheerder kompenseer baie goed vir lastrappe en vergelyk ook goed met 'n ander spanningsbeheermetode wat prakties ge-evalueer is.
80

A multilevel inverter for DC reticulation

Molepo, Seaga Abram 03 1900 (has links)
Thesis (MScEng)--Stellenbosch University, 2003. / ENGLISH ABSTRACT: This report presents the design and development of a multilevel inverter for DC reticulation. Two main multilevel inverter topologies are introduced and discussed. The research focusses on the flying capacitor multilevel topology, since it became evident that it is more suitable for DC reticulation than the diode clamped multilevel topology. A bootstrap power supply for the gate drive circuits of a multilevel inverter is developed and its feasibility verified experimentally. A self-starting auxiliary power supply, that aims at addressing the power supply problem of DC to AC and DC to DC converters, is designed and its functionality demonstrated on a flying capacitor multilevel inverter. An FPGA based digital controller for implementing the inverter's control algorithms is also discussed. This controller incorporates a feed-forward output voltage regulation technique. Experimental results obtained with the four-level flying capacitor multilevel inverter, using the FPGA based digital controller and the self-starting auxiliary power supply, are presented in this report. / AFRIKAANSE OPSOMMING: In hierdie verslag word die ontwerp en ontwikkelling van 'n multivlak omsetter vir GS retikulasie bespreek. Twee hoof multivlak omsetter topologië word voorgestel en bespreek. Die navorsing fokus op die "vlieënde-kapasitor" multivlak topologië omdat dit duidelik geword het dat dit 'n beter opsie is vir die GS retikulasie as die diode-klamp multivlak topologië. 'n Kragbron vir die hekaandryfbane van die multivlak omsetter is ontwikkel en die werking daarvan is met experimentele toetse bevestig. 'n Self-begin kragbron, wat die probleem van die kragtoevoer aan die GS na WS en die GS na GS omsetters aanspreek, is ontwerp en die funksionaliteit is gedemonstreer met die "vlieënde-kapasitor" multivlak . omsetter. 'n Digitale beheerder, gebaseer op 'n FPGA, wat gebruik word om die omsetter se beheer algoritmes te implementeer, word ook bespreek. Hierdie beheerder inkorporeer 'n vorentoe-voer uittree spannings regulasie tegniek. Eksperimentele resultate wat gekry is met 'n vier-vlak "vlieënde-kapasitor" multivlak omsetter, wat van die FPGA gebaseerde digitale beheerder en die self-begin kragbron gebruik maak, word ook in die verslag bespreek.

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