Thesis (MScEng (Electrical and Electronic Engineering))--University of Stellenbosch, 2010. / ENGLISH ABSTRACT: The use of power electronic converters provides a more efficient, accurate and dynamic solution to reactive compensation. In this thesis the application of power electronic converters to shunt reactive compensation will be discussed. In particular voltage dips and voltage unbalance are considered as both can be mitigated by means of shunt reactive compensation. A pre-existing uninterruptible power supply is adapted to operate as a shunt reactive compensator. The uninterruptible power supply consists of a 250 kVA three phase voltage source inverter. The modifications are limited to software and control algorithms that do not alter the normal operation of the uninterruptible power supply. Control algorithms are designed and discussed in detail. A typical double loop control strategy is implemented on the power electronic converter. The inner loop consists of a dead-beat current controller. The outer loop consists of three proportional and integral controllers controlling the DC-bus voltage, AC voltage and voltage unbalance respectively. Voltage dips and unbalance are compensated for using only reactive power. Focus is placed on producing a result can be used easily in practice. / AFRIKAANSE OPSOMMING: Drywings elektroniese omsetters wat gebruik word vir newe reaktiewe kompensasie lewer meer effektiewe, akkurate en dinamiese resultate. In hierdie tesis word die toepassing van drywings elektroniese omsetters vir newe reaktiewe kompensasie bespreek. Daar word meer spesifiek na spannings duike en spannings wanbalans gekyk aangesien albei met newe reaktiewe kompensasie verminder kan word. ’n Bestaande nood kragbron is aangepas om as n newe reaktiewe kompenseerder te funksioneer. Die nood kragbron bestaan hoofsaaklik uit ’n 250 kVA drie fase omsetter spanningsbron. Die aanpassings is beperk tot sagteware en beheer algoritmes wat nie die oorspronklike funksionaliteit van die nood krag bron beinvloed nie. Beheer algoritmes word ontwerp en deeglik bespreek. ’n Tipiese dubbel lus beheer strategie word op die drywings elektroniese omsetter toegepas. Die binnelus bestaan uit ’n voorspellende stroom beheerder. Die buite-lus bestaan uit drie proportioneel en integraal beheerders wat onderskeidelik die GS-bus spanning, WS spanning en spanning wanbalans reguleer. Spannings duike en wanbalans is verminder deur slegs reaktiewe drywing te gebruik. Die doel was ook om ’n prakties bruikbare resultaat te lewer.

Synchronous buck converter based multiphase architectures are evaluated to determine whether or not the most widespread voltage regulator topology can meet the power delivery requirements of next generation computer microprocessors. According to the prognostications, the load current will rise to 200A along with the decrease of the supply voltage to 0.5V and staggering tight dynamic and static load line tolerances. In view of these demands, researchers face serious challenges to bring forth compliant solutions that can further offer acceptable conversion efficiencies and minimum mainboard area occupancy. Among the most prominent investigation fronts are those surveying fundamental technology improvements aiming at making power semiconductor devices more effective at high switching frequency. The latter is of critical importance as the increase of the switching frequency is fundamentally recognized as the way forward to enhance power density conversion. Provided that switching losses must be kept low to enable the miniaturization of the filter components, one primary goal is to cope with semiconductor and system integration technologies enabling fast dynamic operation of ultra-low ON resistance power switches. This justifies the main focus of this thesis work, centered around a comprehensive analysis of the MOSFET switching behavior in the synchronous buck converter. The MOSFETs dynamic operation, far from being well describable with the traditional clamped inductive hard-switching mode, is strongly influenced by a number of frequently ignored linear and nonlinear parasitic elements that must be taken into account in order to fully predict real switching waveforms, understand their dynamics, and most importantly, identify and quantify the related mechanisms leading to heat generation. This will be revealed from in-depth investigations of the switched converter under fast switching speeds and heavy load. Recognizing the key relevance of appropriate modeling tools that support this task, the second focal point of the thesis aims at developing a number of suitable models for the switching analysis of power MOSFETs. Combined with a series of design guidelines and optimization procedures, these models form the basis of a proposed methodological approach, where numerical computations replace the usually enormous experimental effort to elucidate the most effective pathways towards reducing power losses. This gives rise to the concept referred to as virtual design loop, which is successfully applied to the development of a new power MOSFET technology offering outstanding dynamic and static performance characteristics. From a system perspective, the limits of the power density conversion will be explored for this and other emerging technologies that promise to open up a new paradigm in power integration capabilities.

The Masters Thesis research focuses on reactive power and voltage control during and following major power system disturbances such as faults and subsequent loss of transmission line(s) or generator(s), voltage recovery phenomena following successful fault clearing, dynamic swings of power systems and local voltage suppression, etc. During these events, load and other system dynamics may cause reactive power deficiencies and system voltage issues such as delayed voltage recovery. These phenomena may lead to secondary events such as tripping of loads and/or circuits. Dynamic VAr sources such as generators, static VAr compensators (SVCs), STATCOMs etc and to a lesser degree static VAr sources such as capacitor or reactor banks, can help the system recover from these contingencies by providing fast modulation of the reactive power. Because of the higher cost of dynamic VAr resources, it is important to optimize the deployment of these devices by minimizing the total installed capacity of dynamic VAR resources while meeting the technical requirement and achieving the necessary performance of the system. We refer to this problem as the optimal allocation of dynamic VAR sources (OAODVARS). OAODVARS has been addressed with traditional analytic methods as well as with Artificial Intelligence methods such as genetic algorithms and Tabu search using mostly power flow type models. Both type of methods, as reported in the literature, have not provided satisfactory solutions because they ignore system dynamics and especially load dynamics, in other words they are based on power flow type models. In addition the AI methods have been proved to be extremely inefficient. We propose a new approach that has the following two advantages: (a) it is based on a realistic model that captures system dynamics and (b) it is based on the efficient successive approximation dynamic programming. The solution is provided as a sequence of planning decisions over the planning horizon. The proposed method will be demonstrated on the IEEE 24-bus reliability test system.

This research work deals with the application of the phase shifting transformer in improving the steady state performance and voltage stability of transmission network that has transmission lines at different voltage levels running in parallel to each other. Transmission power system networks are usually developed using lines built at a certain voltage level initially. As power demand requirements increase, building of the new lines at the same voltage level becomes necessary. However, lesser and lesser improvements in transfer capacity are realised when the additional lines are built. This prompts utilities to consider higher voltages for future lines as these have a higher transfer capacity. Utilities usually lay, i.e., they build in parallel, newer, higher voltage transmission lines along side the existing lower voltage ones. Power flow in power system is mainly influenced by impedances of equipment. If the combined impedance of the existing, lower voltage transmission system is relatively less than the impedance of the newer, higher voltage ones, power may primarily flow through it rather than via the newer, parallel higher voltage transmission network. This may lead to a serious underutilisation of the newer infrastructure with a higher transmission capacity. Transmission networks similar to the one described above are common throughout the world. This study was undertaken towards finding solutions to the problem of under utilisation of such transmission lines. The study was performed by first reviewing the literature on the use of phase shifting transformers to redirect power flow in transmission networks throughout the world. This was followed by analysis of the theory on how and what determines the power flow in power networks. Several simulations of varying the phase of the phase shifting transformer were performed on the Cape network, as a case study, to investigate the impact on the power flow distribution and voltage stability performance of the 765 kV and 400 kV transmission lines carrying power to the Western Cape. In this dissertation, it has been demonstrated that a phase shifting transformer can be used to alter the power flow patterns so that power flows are restructured or redistributed, such that power which originally flowed via the low impedance, lower voltage system is transferred to the parallel higher voltage transmission system of lines. It is shown that once the power flows are redistributed, steady state and voltage stability performance of the total system can be enhanced and an increase in its power transfer capacity can be realised. / Thesis (M.Sc.Eng.)-University of KwaZulu-Natal, Durban, 2011.

Thesis (MEng)--University of Stellenbosch, 2000. / ENGLISH ABSTRACT: Recent advances in semiconductor device development pushed a large number of network devices onto the market. These devices can solve network problems more effectively and economically than ever before. Network planners need tools to analyse and implement such devices to help solve the largest network problem in South Africa: voltage regulation. Rural networks experience the majority of voltage-regulation problems in South Africa. The networks are long sub-transmission and reticulation networks and are modelled by two generic networks, namely a radial network and a two-source ring network. The equations describing voltage regulation for the generic networks are developed and implemented in PSAT, a software analysis tool. The voltage regulation for two case studies that represent the two generic networks are analysed. Four generic network devices are defined and various control methods for these devices are developed to solve the network problem. The aim of PSAT is to help the network planner to quickly evaluate a number of possible solutions and to choose the best solution for further studies. This is demonstrated with the aid of the case studies. PSAT provides a sturdy platform on which future developments, such as stability analyses, can be built. However, PSAT can already function as a stand-alone analysis tool to solve voltage regulation as a network problem. / AFRIKAANSE OPSOMMING: Onlangse vooruitgang in halfgeleier ontwikkeling het 'n groot aantal netwerktoestelle op die mark geplaas. Hierdie toestelle kan netwerk probleme doeltreffender en meer ekonomies oplos as ooit vantevore. 'n Behoefte aan 'n pakket wat netwerkbeplanners in staat stelom die netwerktoestelle te analiseer, is geïdentifiseer. So 'n pakket sal hulle help om die vernaamste netwerkprobleem in Suid-Afrika, nl. spanningsregulasie, op te los. Die oorgrote meerderheid spanningsregulasie probleme word op die platteland ondervind. Plattelandse netwerke word gekenmerk deur lang sub-transmissie en retikulasie netwerke. Hierdie netwerke word met behulp van twee generiese netwerke gemodelleer. 'n Radiale netwerk en 'n dubbelbron ringnetwerk word aangewend om enige plattelandse netwerk te analiseer. Vergelykings is vir spanningsanalise ontwikkel en in PSAT, 'n analitiese sagteware pakket, geïmplementeer. Twee gevallestudies is gedoen om die twee netwerke afsonderlik voor te stel en die vergelykings van PSAT te evalueer. Alle netwerktoestelle is in een van vier generiese kategorieë geklassifiseer. Modelle is vir elk van die kategorieë ontwikkel vtr spanningsregulasie analise. Die doel van PSAT is om die netwerk beplanner te help om vinnig en effektief soveel moontlik opsies te ondersoek as oplossings vir 'n spesifieke netwerk probleem. PSAT is reeds 'n alleenstaande pakket wat in die toekoms uitgebrei sal word om na die analise van stabilitietsprobleme te kyk.

Thesis (MScEng)--University of Stellenbosch, 2001. / ENGLISH ABSTRACT: This thesis covers the development of a multilevel cascaded inverter for the purpose of costeffective transformerless series dip compensation. Of all known power quality problems, voltage dips are the greatest reason for concern. Dips/sags occur more frequently than outages and therefore tend to be more costly for industry as modem technical equipment becomes all the more sensitive to the quality and reliability of supply. A number of devices already exist to compensate for this problem, but the cost of most of these systems does not always justify the financial losses they compensate for. All of these systems are using transformers and/or large filter components that contribute to the size, price and losses to quite a large extent. Series injection dip compensators offer the advantage of only having to compensate for the decrease in supply voltage during a dip. This results in a significant reduction in the converter ratings and energy storage requirements compared to conventional uninterruptible power supplies or shunt injection power quality devices. Existing inverter topologies, including multilevel inverters, were therefore studied and compared as possible solutions for cost-effective transformerless series dip compensation. On the basis of these considerations the multilevel cascaded inverter seems to be the most cost-effective option. The relatively low harmonic content of its unfiltered output also eliminates the need for a large output filter. A single-phase dip compensator, with this topology, was designed and built according to specifications stated by Eskom, the main utility in South Africa. Batteries as energy storage and automotive MOSFETs as switching components, proved to be most cost-effective options for the specified power ratings. Control algorithms for dip compensation with the multilevel inverter were also developed. Some of these algorithms are based on existing techniques, but two new algorithms were also developed to implement force commutation of the thyristors and to share the power dissipation in the dip compensator. Simulations indicated that these algorithms could be suitable and sufficient for their application. This dip compensator with its control algorithms was tested with a dip generator, developed at the University of Stellenbosch, for different types of loads. The experimental results confirmed the simulations and showed a very good performance for the specified conditions. An optimised design of this dip compensator will make it a cost-effective solution for dip compensation. / AFRIKAANSE OPSOMMING: Hierdie tesis dek die ontwikkeling van 'n multivlakwisselrigter, in kaskade, met koste-effektiewe transformatorlose duik kompensasie as mikpunt. Van al die bekende toevoerkwaliteit probleme wek duike in die spanning die meeste kommer. Duike kom meer gereeld voor as kragonderbrekings en neig daarom om 'n groter onkoste te wees vir die industrie soos wat moderne tegnologiese toerusting al hoe meer sensitief raak vir die kwaliteit en betroubaarheid van die toevoer. 'n Aantal toestelle wat vir hierdie probleem kompenseer bestaan reeds, maar die koste van hierdie stelsels regverdig nie altyd die finansiële verliese wat hulle moet elimineer nie. Al hierdie stelsels gebruik transformators en/of groot filter komponente wat grootliks bydra tot die grootte, prys en verliese van hierdie stelsels. Serie-injeksie kompenseerders het die voordeel dat hulle net kompenseer vir die verlies in die toevoerspanning tydens die duik. Dit het 'n beduidende vermindering in die omsetterkenwaardes en energiestoorvereistes tot gevolg in vergelyking met ononderbroke kragbronne (UPS) of newe-injeksie toevoerkwaliteit toestelle. Daarom IS bestaande wisselrigtertopologië, insluitende multivlakwisselrigters, bestudeer en vergelyk as moontlike oplossings vir koste-effektiewe serie duik-kompensasie. Van al hierdie moontlikhede lyk die multivlakwisselrigter, in kaskade, na die mees koste-effektiewe opsie. Die relatiewe lae harmoniese inhoud van sy ongefilterde uittree elimineer die behoefte aan 'n groot uittreefilter. 'n Enkelfase duik kompenseerder, met hierdie topologie, is ontwerp en gebou volgens die spesifikasies wat vasgestel is deur Eskom, die hoof elektriese kragvoorsiener in Suid-Afrika. Dit het geblyk dat batterye, en MOSFETte uit die motorbedryf, die mees koste-effektiewe opsies bied vir onderskeidelik die energiestoor en skakelkomponente. Beheeralgoritmes VIr duik kompensasie met die multivlakwisselrigter is ook ontwikkel. Sommige van hierdie algoritmes is gebaseer op bestaande tegnieke, maar twee nuwe algoritmes is ook ontwikkel vir die kommutering van die tiristors en die deling van die drywingsverkwisting in die duik kompenseerder. Simulasies dui aan dat hierdie algoritmes geskik en voldoende kan wees vir hulle toepassing. Hierdie duik kompenseerder met sy beheeralgoritmes is getoets vir verskillende tipes laste met 'n duikgenerator wat ontwikkel is by die Universiteit van Stellenbosch. Die eksperimentele resultate bevestig dit wat verkry is uit die simulasies en wys 'n goeie werkverrigting vir die gespesifiseerde kondisies. 'n Geoptimeerde ontwerp van hierdie duik kompenseerder sal dit 'n koste-effektiewe oplossing maak vir duik kompensasie.

CAPES / Este trabalho apresenta um sistema eletrônico com entrada universal utilizando um retificador SEPIC não isolado para fornecer e controlar a corrente de LEDs de potência. Um Snubber regenerativo que reduz as perdas de comutação e melhora a eficiência do sistema é proposto. Para realizar a dimerização, bem como reduzir a ondulação da corrente nos LEDs, um regulador linear de corrente é conectado na saída do conversor SEPIC. A utilização do regulador linear também permite que o conversor opere com entrada universal sem a utilização de circuitos adicionais. Para evitar perdas excessivas, o regulador é configurado para operar na região limiar da regulação. O ponto de perda mínimo do regulador é ajustado através de um circuito detector de mínimo com o sistema operando em malha fechada. As etapas de operação, as formas de onda e as principais equações do snubber regenerativo aplicado ao SEPIC são descritas no trabalho. Para verificar e validar a análise teórica são apresentados dois protótipos com potências de saída de 42 W e 145 W, variando de 15% a 100%, para o conversor operando com tensão de entrada de 90 a 240 V e alimentado 35 LEDs conectados em série. / This paper presents a universal-input AC electronic lighting system using a non-isolated SEPIC PFC rectifier to drive and control power LEDs currents. One energy regenerative snubber for reducing the converter switching losses and improve the system efficiency is proposed. The dimmable flicker-free current in the LEDs array is obtained through a linear current regulator placed in the SEPIC’s output terminals. In order to reduce the efficiency impairment, the conditions for achieving minimum energy loss in the current regulator are also detailed. Point of minimum energy loss in the linear regulator is adjusted through valley detector circuit in closed loop system operation. The operation stages as well as the theoretical waveforms and main equations at steady state of the proposed SEPIC rectifier using the regenerative snubber are described. To verify the theoretical analysis carried out, experimental results of two prototypes (42 W and 145 W) operating from 90 to 240 V and output power from 15 to 100% for 35 LEDs are also presented.

CAPES / Este trabalho apresenta um sistema eletrônico com entrada universal utilizando um retificador SEPIC não isolado para fornecer e controlar a corrente de LEDs de potência. Um Snubber regenerativo que reduz as perdas de comutação e melhora a eficiência do sistema é proposto. Para realizar a dimerização, bem como reduzir a ondulação da corrente nos LEDs, um regulador linear de corrente é conectado na saída do conversor SEPIC. A utilização do regulador linear também permite que o conversor opere com entrada universal sem a utilização de circuitos adicionais. Para evitar perdas excessivas, o regulador é configurado para operar na região limiar da regulação. O ponto de perda mínimo do regulador é ajustado através de um circuito detector de mínimo com o sistema operando em malha fechada. As etapas de operação, as formas de onda e as principais equações do snubber regenerativo aplicado ao SEPIC são descritas no trabalho. Para verificar e validar a análise teórica são apresentados dois protótipos com potências de saída de 42 W e 145 W, variando de 15% a 100%, para o conversor operando com tensão de entrada de 90 a 240 V e alimentado 35 LEDs conectados em série. / This paper presents a universal-input AC electronic lighting system using a non-isolated SEPIC PFC rectifier to drive and control power LEDs currents. One energy regenerative snubber for reducing the converter switching losses and improve the system efficiency is proposed. The dimmable flicker-free current in the LEDs array is obtained through a linear current regulator placed in the SEPIC’s output terminals. In order to reduce the efficiency impairment, the conditions for achieving minimum energy loss in the current regulator are also detailed. Point of minimum energy loss in the linear regulator is adjusted through valley detector circuit in closed loop system operation. The operation stages as well as the theoretical waveforms and main equations at steady state of the proposed SEPIC rectifier using the regenerative snubber are described. To verify the theoretical analysis carried out, experimental results of two prototypes (42 W and 145 W) operating from 90 to 240 V and output power from 15 to 100% for 35 LEDs are also presented.

Orientadores: Jacobus Willibrordus Swart, Jader Alves de Lima Filho / Dissertação (mestrado) - Universidade Estadual de Campinas, Faculdade de Engenharia Eletrica e de Computação / Made available in DSpace on 2018-08-15T17:45:20Z (GMT). No. of bitstreams: 1 ZampronhoNeto_Fernando_M.pdf: 5842798 bytes, checksum: 248329a719c06d1a00d97f94590f1b92 (MD5) Previous issue date: 2009 / Resumo: Este trabalho tem como objetivo o estudo de uma arquitetura de regulador de tensão do tipo multi-fase para alimentação de microprocessadores, os quais demandam pequena variação em sua tensão, mesmo face aos seus agressivos transitórios de corrente. O estudo engloba a análise, que descreve as vantagens e desvantagens de topologias de reguladores chaveados, o projeto, a simulação, a fabricação e a caracterização experimental do regulador. Na etapa de projeto, uma nova abordagem no dimensionamento do filtro externo LC é apresentada, considerando-se seus respectivos elementos parasitas, a partir da introdução do parâmetro .fator de não idealidade., ou n, que é compreendido no intervalo [0, 1]. Quanto mais n se aproxima da unidade, menores serão os elementos parasitas do filtro, facilitando a escolha dos capacitores e indutores no mercado. Adicionalmente, é proposta uma técnica de projeto do compensador em freqüência, aplicada em topologias realimentadas por tensão. Esta consiste na soma de sua tensão de saída com a diferença de potencial entre dois de seus nós internos, que ocorre apenas durante o transitório de carga, reduzindo o tempo de resposta do regulador. Simulações mostraram uma queda de mais de 25% na ondulação da tensão de carga utilizando esta técnica, em comparação com a solução convencional. O processo, simulador e modelos utilizados neste trabalho são, respectivamente, o AMS H35, PSPICE e Bsim3v3. O layout do regulador foi feito via Mentor Graphics e possui área efetiva de 0,444mm2. A fabricação na foundry AMS foi viabilizada pelo programa multi-usuário da FAPESP. A caracterização experimental compara o tempo de resposta do regulador nas mesmas condições da etapa de simulação. Resultados experimentais indicaram uma redução de 96,1% na ondulação da tensão de carga durante seu transitório de corrente utilizando a técnica proposta, em comparação a solução convencional, validando a nova técnica de projeto do compensador em freqüência. O presente trabalho é concluído enfatizando-se os objetivos alcançados e principais resultados experimentais obtidos, dificuldades de projeto e limitações da arquitetura do regulador chaveado estudada / Abstract: This work aims to study the topology of multi-phase voltage regulators applied to microprocessors, where only tiny variations in the supply voltage are allowed, even when facing aggressive current transients. This study consists in the analysis, which describes the advantages and disadvantages of switched voltage regulator topologies, design, simulation, layout and experimental characterization of the proposed regulator. In the design phase, a new approach in sizing the external LC filter is herein described, considering their stray elements, through the introduction of the .non ideality. parameter, or n, which is valid within interval [0,1]. As more as n approaches unity, less parasitic elements the filter will have, easing the choice of the capacitors and inductors commercially available. In addition to this, a new technique applied to voltage feedback topologies is proposed, which consists in adding the output voltage of the frequency compensator to a voltage between two of its internal nodes. With such an approach, the response time of the regulator to load transients decreases. Simulation results show a reduction over 25% in the output voltage ripple using this new approach, when comparing to the traditional solution. The process, simulator and models used in this work are, respectively, AMS H35, PSPICE and Bsim 3v3. The layout of the regulator was edited through Mentor Graphics, and it has an effective area of 0.444mm2. The fabrication in foundry AMS was done by multi-user program of FAPESP. The experimental characterization compares the response time of the regulator in the same conditions of simulation phase. Experimental results indicated a 96,1% reduction in load voltage ripple during transient, when comparing the purposed technique with the traditional solution, validating the excellent performance of the regulator with the new design technique. This work is concluded by emphasizing the reached objectives and main experimental results reached, design difficulties and limitations of the switched-regulator architecture studied / Mestrado / Eletrônica, Microeletrônica e Optoeletrônica / Mestre em Engenharia Elétrica

Orientadores: Jacobus Willibrordus Swart, Jader Alves de Lima Filho / Dissertação (mestrado) - Universidade Estadual de Campinas, Faculdade de Engenharia Eletrica e de Computação / Made available in DSpace on 2018-08-15T22:10:27Z (GMT). No. of bitstreams: 1 Mansano_AndreLuisRodrigues_M.pdf: 2816553 bytes, checksum: 2746391c004342d1e0c2d8c4c2f507e8 (MD5) Previous issue date: 2009 / Resumo: Neste trabalho de Mestrado, foi projetado um conversor DC/DC charge-pump (CP) duplicador de tensão para corrente de carga máxima de 20mA, e que necessita de circuitos de controle para o apropriado acionamento das chaves, regulação de tensão e proteção do estágio duplicador de tensão. O sistema de controle projetado é composto por um circuito de regulação linear (CRL), um regulador Skip, um limitador de corrente (LC) e um circuito de bootstrapping (BOOT) que auxilia o acionamento do estágio duplicador. CP corresponde ao estágio de potência do sistema que faz interface direta com a carga, sendo sua tensão de entrada (PVIN) nominal no valor de 1,5V. O trabalho objetiva obter um conversor DC/DC funcional (demonstrado por resultados de Silício) atingindo resultados experimentais com o menor desvio possível comparados aos valores simulados durante o projeto. A tensão simulada de saída (VOUT), a vazio (sem carga), é 3V. Para carga máxima DC (20mA), o valor de VOUT simulado é de 2,4V. O circuito BOOT gera uma tensão na faixa de 4,5V - 5V, para uma carga DC de 1mA. A corrente limitada pelo bloco LC no circuito duplicador é 30mA. O CLR gera uma tensão inversamente proporcional a VOUT, tendo seus limites mínimo e máximo de 1,3V e 5,2V, respectivamente. Todo o sistema foi integrado no processo de fabricação AMS 0.35um HV, exceto os capacitores do estágio duplicador e do circuito de bootstrapping que são externos. Os resultados experimentais mostram desvio (comparados com simulação) de -12,5% em VOUT @ 20mA DC e -0,13% sem carga, -6% à saída de BOOT @ 1mA DC, +23% CLR mínimo, -3,85% em CRL máximo e +10% na corrente limitada. Durante o desenvolvimento deste trabalho, o Circuito de Regulação Linear (CRL) foi publicado no SBCCI 2009 apresentando sua rápida resposta à transientes de carga, o que é sua grande vantagem comparado a circuitos anteriormente propostos / Abstract: In this work, a DC/DC charge-pump voltage-doubler converter, for maximum load current of 20mA, was designed and fabricated. The Charge Pump (CP) needs control circuits for properly switching, voltage regulation and protection of voltage doubler stage. The control system designed comprises a linear regulation circuit (CRL), a Skip mode regulator, current limitation circuit (LC) and a bootstrapping circuit (BOOT), which provides the appropriate voltage to turn on CP power transistors. The voltage doubler is the power stage that interfaces directly to the load and its nominal input voltage PVIN is 1.5V. The objective of this work is to guarantee that the proposed DC/DC converter works properly (proved by Silicon results) and to achieve experimental results with the least deviation possible compared to simulation. The nominal output voltage (VOUT) with no load is 3V. For maximum DC load (20mA), simulated VOUT is 2.4V. BOOT circuit provides voltage within 4.5V - 5V for DC current load of 1mA. The LC limits the drawn current through the voltage-doubler at 30mA. The CRL provides a control voltage inversely proportional to VOUT and its minimum and maximum are 1.3V and 5.2V respectively. The whole system has been integrated in AMS 0.35um HV except the capacitors of CP and BOOT circuits. The experimental results show deviation (comparing to simulation) of -12,5% on VOUT @ 20mA DC and -0,13% @ no load , -6% on BOOT output @ 1mA DC, +23% CLR minimum, -3,85% CRL maximum and +10% on LC circuit. During the development of this work, the CRL circuit has been published in the SBCCI 2009 conference to present its fast-response to stringent load transient which is the biggest CRL advantage compared to previously proposed circuits / Mestrado / Mestre em Engenharia Elétrica