Thesis (M.S.)--Oregon State University, 2005. / Printout. Includes bibliographical references (leaves 86-87). Also available on the World Wide Web.

Thesis (M.S.)--Oregon State University, 2004. / Typescript (photocopy). Includes bibliographical references (leaves 45-48). Also available on the World Wide Web.

Thesis (Ph. D.)--Virginia Polytechnic Institute and State University, 1993. / Vita. Abstract. Includes bibliographical references (leaves 128-135). Also available via the Internet.

Thesis (M.E.)--University of Canterbury, 2007. / Typescript (photocopy). "09 July 2007." Includes bibliographical references. Also available via the World Wide Web.

Thesis (M.E.)--University of Canterbury, 2006. / Typescript (photocopy). "March 2006." Includes bibliographical references (p. 171-179). Also available via the World Wide Web.

D.Ing. / In this dissertation a pulsed DC voltage bus comprising a full wave rectified sinusoidal voltage will be investigated for use as a link voltage. A background study into existing converter topologies for single phase uninterruptable power supplies and three phase front end converters, applicable to the study, is discussed. The definition of the bus voltage will be given as well as the power handling limitations. An experimental 3.3kW single phase UPS and a 3.3kW three phase front end converter using the bus was designed, built, tested and the results presented. The design and modelling of the two systems are discussed so as to clarify the advantages, disadvantages and limits of using such a bus. The appropriate standards pertaining the two converter systems have been looked up and the impact on the design discussed. The discussion will be concluded with a summarisation and possible future work is discussed.

A modern system-on-chip (SoC) integrates a range of analog, digital, and mixed-signal building blocks, each with a dedicated voltage domain to maximize energy efficiency. On-chip low-drop-out regulators (LDOs) are widely used to implement these voltage domains due to their advantages of high power density and the ease of integration to a complementary metal-oxide-semiconductor (CMOS) process. Recently, digital LDOs have gained large attention for their low input voltage support for emerging sub-mW SoCs, portability across designs, and process scalability. However, some of the major drawbacks of a conventional digital LDO design are (i) the trade-off between control loop latency and power dissipation which demands a large output capacitor, (ii) failure to address the performance degradations caused by the parasitics in a practical power grid, and (iii) insufficient power-supply-rejection-ratio (PSRR) and large ripple in the output voltage. Chapters 2 through 4 of this thesis present my research on the design and circuit techniques for improving the aforementioned challenges in fully-integrated digital LDOs. The first work implements a hybrid event- and time-driven control in the digital LDO architecture to improve the response and settling time-related metrics over the existing designs. The second work presents a power delivery system consisting of 9 distributed event-driven digital LDOs for supporting a spatially large digital load. The proposed distributed LDO design achieves large improvements in the steady-state and non-steady-state performances compared to a single LDO design. In the third work, we prototype a digital LDO based on new current-source power-FETs to achieve a high PSRR and low output voltage ripple. Lastly, on-chip voltage regulators have recently found usefulness in hardware security applications. An on-chip LDO can be used to improve the side-channel attack (SCA) resistance of a cryptographic core with design modifications to the classical LDO architecture. However, the existing designs incur non-negligible overheads in performance, power, and silicon area due to the conventional active-for-all-encryption-rounds architecture. In the last chapter, we propose a detection-driven activation technique to achieve a near-zero energy-delay-product (EDP) overhead in a SCA resilient digital LDO. In this architecture, the LDO can detect an attack attempt and enable SCA protection only if an attack is detected.

[pt] Neste trabalho é estudado um meio de se determinar os parâmetros de um regulador de tensão. È também discutida a determinação do modelo para o regulador. São mostrados exemplos diferentes aos reguladores de ação não contínua. Foi desenvolvido um programa digital para simular os testes de campo realizados com os reguladores. / [en] A study is made of a way of determining the parameters of a voltage regulator. Some thoughts are also given on the determination of the model representing the regulator. Sample cases are given for the noncontinuosly acting regulators. A digital program was developed for simulating the tests that were with the regulators.

[pt] As técnicas que usam programas digitais clássicos para análise dos modos instáveis de oscilação em sistemas multimáquinas, não seguem, via de regra, uma metodologia geral e rigorosa que permita identificar, sem muitas tentativas, máquinas ou grupos de máquinas são mais efetivas para a aplicação de sinais suplementares nos sistemas reguladores de tensão, com o fim de prover o necessário amortecimento ao sistema quando sujeito a perturbações. Este trabalho tentará desenvolver a aplicação de dois métodos para tal tipo de análise, sendo um prático, baseado em teste facilmente executáveis com os programas digitais clássicos, e outro, analítico, que mediante o emprego de autovalores e através de uma análise da sensibilidade permita que sejam identificadas suplementares para amortecimento dos modos de oscilação. Em conseqüência, será também abordado o ajuste dos sinais estabilizadores, porquanto, conforme procurar-se-á demonstrar, o método propiciará meios de torná-los mais efetivos para uma larga faixa de operação do sistema. / [en] The practices normally used in classical digital programs for oscillation mode analysis in dynamically unstable multimachine systems, do not use, in such way a general methodology that allows identification, without a great deal of trial and error, wich machines, are more effectives in providing damping to the system through suplementary signal application in excitation controls. This work attempts to describe methods for application of analysis based on tests that can be easily executed whith classical digital programs. Also a method based on eigenvalues and eigenvectores sensitivity analysis is presented. This method uses eigenvectors to find the groups of coherent machines. To give insight into the relationships between a give machine damping and the particurlar frequency of oscilation, the eigenvalue analysis is used. Techniques for speed stabilizers adjustments are shown to provide performance over a wide range of systems conditions.

The microprocessor faces a big challenge of heat dissipation. In order to enhance the performance of the microprocessor without increasing the heat dissipation, the leading microprocessor company, Intel, uses several methods to reduce the power consumption. Theses methods include enhanced sleep states control, the Speed Step technology, and multi-core architecture. These are closely related to the Voltage Regulator (VR), a dedicated power supply for the microprocessor and its control method. The speed of the VR control system should be high in order to meet the stringent load-line requirements with the high current and high di/dt, otherwise, a lot of decoupling capacitors are necessary. Capacitors make the VR cost and size higher. Therefore, the VR control method is very important. This dissertation discusses the way to increase the speed of VR without degrading other functions, such as the system efficiency, and the required control functions (AVP, current sharing and interleaving). The easiest way to increase the speed of the VR is to increase the switching frequency. However, higher switching frequency results in system efficiency degradation. This paper uses two approaches to deal with this issue. The first one is the architecture approach. The other is the fast transient control approach. For the architecture approach, a two-stage architecture is chosen. It is already shown that with a two-stage architecture, the switching frequency of the second stage can be increased, while keeping the same system efficiency. Therefore with the two-stage architecture, a high performance VR can be easily implemented. However, the light-load efficiency of two-stage architecture is not good because the bus voltage is designed for the full-load efficiency which is not optimized for the light load. The light-load efficiency is also important factor and it should be maximized because it is related to the battery life of mobile application or the energy utilization. Therefore, Adaptive Bus Voltage Positioning (ABVP) control has been proposed. By adaptively adjusting the bus voltage according to the load current, the system efficiency can be optimized for whole load range. The bus voltage rate of change is determined by the first stage bandwidth. In order to maintain regulation during a fast dynamic load, the first stage bandwidth should be high. However, it is observed from hardware when the first stage bandwidth is higher, the ABVP system can become unstable. To get a stable system, the first stage bandwidth is often designed to be slow which causes poor ABVP dynamic response. The large number of bus capacitors necessary for this also increases the size and cost. In this dissertation, in order to raise the first stage bandwidth, a stability analysis is performed. The instability loop (TABVP) is identified, and a small signal model to predict this loop is suggested. TABVP is related to the first stage bandwidth. With the higher first stage bandwidth, the peak magnitude of TABVP is larger. When the peak magnitude of TABVP touches 0dB, the system becomes unstable. Two solutions are proposed to reduce this TABVP magnitude without decreasing the first stage bandwidth. One method is to increase the feedforward gain and the other approach is to use a low pass filter. With these strategies, the ABVP system can be designed to be stable while pushing first stage bandwidth as high as possible. The ABVP-AVP system and its design are verified with hardware. For the fast transient control approach hysteretic control is chosen because of its fast transient and high light-load efficiency with DCM operation. However, in order to use the hysteretic control method for multiphase VR applications interleaving must be implemented. In this dissertation, a multiphase hysteretic control method is proposed which can achieve interleaving without losing its benefits. Using the phase locked loop (PLL), this control method locks the phase and frequency of the duty cycles to the reference clocks by modifying the size of the hysteretic band, to say, hysteretic band width. By phase shifting the reference clocks, interleaving can be achieved under steady state. During the load transient, the system loses the phase-locking function due to the slow hysteretic band width changing loop, and the system then reacts quickly to the load change without the interruption from the phase locking function (or the interleaving function). The proposed hysteretic control method consists of two loops, the fast hysteretic control loop and the slow hysteretic band width changing loop. These two nonlinear loops are difficult to model and analyze together. Therefore, assuming these two loops can be separated because of the speed difference, the phase plane model is used for the fast hysteretic control loop and the sampled data model is then used for the slow hysteretic band width changing loop. With these models, the proposed hysteretic control method can be analyzed and properly designed. However, if the transient occurs before the slow hysteretic band width changing loop settles down, the transient may start with the large hysteretic band width and the output voltage peak can exceed the specification. To prevent this, a hysteretic band width limiter is inserted. With the hardware, the proposed hysteretic control method and its design are verified. A two-phase VR with 300kHz switching frequency is built and the output capacitance required is only 860μF comparing to 1600μF output capacitance with the 50kHz bandwidth linear control method. That is about 46% capacitor reduction. The proposed hysteretic control method saturates the controller during the transient and the transient peak voltage is determined by the power stage parameters, the inductance and the output capacitors. By decreasing the inductance, the output capacitors are reduced. However, small inductance results in the low efficiency. In order to resolve this, the coupled inductor is used. With the coupled inductor, the transient inductance can be reduced with the same steady state inductance. Therefore, the transient speed can be faster without lowering down the system efficiency. The proposed hysteretic control method with the coupled inductor can be implemented using the DCR current sensing network. A two-phase VR with the proposed hysteretic control and the coupled inductor is built and the output capacitance is only 660μF comparing to 860μF output capacitance with the proposed hysteretic control only. A 23% capacitor reduction is achieved. And compared to the 50kHz bandwidth linear control method, a 60% capacitor reduction is achieved. / Ph. D.