This thesis proposes a high efficiency driving circuit for multiple light emitting diode (LED) lamps with dimming feature. The driving circuit consists of essentially a high-frequency half-bridge series resonant inverter with multiple output transformers, on which primary windings are connected in series, while secondary sides are loaded by LED lamps rated at different powers with different turn ratios. By controlling the frequency of the inverter, the resonant current as well as the lamp current can be regulated simultaneously. On the other hand, the LED lamps can be dimmed individually by the associated dimming switches with integral cycle control. The tactful circuit ensures a high circuit efficiency owing to less conducting losses and zero-voltage switching (ZVS) operation of the active power switches of the inverter and zero current switching (ZCS) operation of the dimming switches. Two prototype circuits designed for 60 W three RGB LED lamps and 50 W five white light LED lamps have been built and tested to verify the analytical predictions. Experimental results demonstrate that the driving circuit can operate the LED lamps at a high efficiency with a wide dimming range. The lamp power can be dimmed to 10% with frequency control, while whole dimming range can be achieved with integral cycle control. The circuit efficiency with integral cycle control is relatively higher than that with frequency control. The measured efficiencies for the two designed circuit are 93% and 90%, respectively, under the rated powers.

A high-frequency half-bridge series resonant inverter with multiple output transformers is developed for driving multiple cold-cathode fluorescent lamps (CCFLs) with dimming feature. The primary sides of the transformers are connected in series with the resonant inverter to have an identical current, while the secondary sides are loaded by CCFLs with galvanic isolation to each other. To ensure a high circuit efficiency, the active power switches of the inverter are designed to be switched on at zero voltage. The resonant current of the inverter can be regulated by controlling the switching frequency of the inverter, so that all CCFLs can be dimmed simultaneously. On the other hand, the primary sides of the output transformers are associated with parallel switches to dim the CCFLs individually. These dimming switches are operated at a low frequency by integral cycle control with zero current switching (ZCS) to reduce the switching losses. The resonant circuit is tactfully designed to alleviate the variation of the resonant current caused by the switching of dimming switches. A laboratory circuit is built for driving 5 CCFLs. The intended circuit performances are confirmed by test results. The variation of the resonant current is less than 10% when the dimming switches are switching, and the measured efficiency for the circuit is 96.15% under the rated powers.

Conselho Nacional de Desenvolvimento Científico e Tecnológico / A complete study of a topology resulting from a combination of two Forward structures, attached to the same magnetic core of a transformer and operating as a Full-Bridge converter is presented. In order to reduce the switching losses and the electromagnetic interference, a soft commutation cell that provides ZCS commutation of all the switches is implemented. This converter limits the current on the main switches at the load current because diverts the sinusoidal half cycle to a auxiliary switch. This way, a new Double Forward On-Off ZCS was developed. / Um estudo completo de uma topologia, resultante de uma combinação entre duas estruturas Forward, acopladas ao mesmo núcleo magnético de um transformador, e operando como um conversor Full-Bridge, é apresentado. Com o objetivo de reduzir as perdas por chaveamento e a interferência eletromagnética, uma célula de comutação não dissipativa, que fornece uma comutação ZCS para todas as chaves do conversor é implementada. Este conversor limita a corrente nas chaves principais ao valor da corrente nominal, pois desvia o semiciclo senoidal da corrente ressonante para uma chave auxiliar. Deste modo, um novo conversor Duplo Forward On-Off ZCS é obtido. / Mestre em Ciências

Boost dc-to-dc converters have very good source interface properties. The input inductor makes the source current smooth and hence these converters provide very good EMI performance. On account of this good property, the boost converter is also the preferred converter for off-line UPF rectifiers. One of the issues of concern in these converters is the large size of the storage capacitor on the dc link. The boost converter suffers from the disadvantage of discontinuous current injected to the load. The size of the capacitor is therefore large. Further, the ripple current in the capacitor is as much as the load current; hence the ESR specification of the tank capacitor is quite demanding. This is specially so in the emerging application areas of automotive power conversion, where the input voltage is low (typically 12V) and large voltage boost (4 to 5) are desired. The first part of this thesis suggests multi-phase boost converter to overcome the disadvantages of large size storage capacitor in boost converter. Comparison between the specification of single stage and multi-stages is thoroughly examined. Besides the average small signal analysis of N converters in parallel and obtaining an equivalent second order system are discussed. By paralleling the converters the design of closed loop control is a demanding task. To achieve proper current sharing among the stages using current control method is inevitable. Design and implementation of closed loop control of multi-phase boost converter both in analog and digital is the topic of next part of the thesis. Comparison between these two approaches is presented in this part and it will be shown that digital control is more convenient for such a topology on account of the requirement of synchronization, phase shifted operation, current balancing and other desired functions, which will be discussed later in detail. A new direct digital control method, which is simple and fast, is developed. Two different realizations with DSP controller and FPGA controller are considered. In the last part of the thesis a novel soft switching circuit for boost converter is presented. It provides Zero Voltage Switching (ZVS) for the main switch and Zero Current Switching (ZCS) for the auxiliary switch. The paper presents the idealized analysis giving all the circuit intervals and the equations necessary for the design of such a circuit. The proposed soft switching circuit is particularly suited for the tapped-inductor boost circuit with a minimum number of extra components. Extension of the method to tapped inductor boost converter addresses the application of Zero Voltage Transition (ZVT) to high conversion ratio converters. Extension of the method to multiphase boost converter shows that with less number of auxiliary switches soft switching operation can be achieved for all interleaved switching devices. Several laboratory prototype boost converters have been built to confirm the theoretical results and design methods are matching with both simulation and experimental results.

With the increasing demand for fast, cheaper, and efficient power converters come the need for a single-stage power factor correction (PFC) converter. Various single-stage PFC converter proposed in the literature has the drawback of high DC bus voltage at the input side and together with the shift to wide bandgap switches like GaN drives the converter cost higher. However, an interleaved topology with high-frequency isolation was proposed in this research work due to the drastic reduction in the DC bus voltage and extremely low input current ripple thereby making the need for an EMI filter circuit optional.   Meanwhile, this research work focuses on adapting the proposed topology for a high voltage low current application (EV charger - 400V, 7KW) and low voltage high current application (telecom power supply - 58V,  58A) owing to cost benefits. However, all single-stage PFC are faced with the drawback of second-order (100Hz) output harmonic ripple. Therefore, the design and simulation presented a huge peak to peak ripple of about 50V/3A and 26V/26A for the EV charger and telecom power supply case, respectively. This created the need for the design of a ripple cancellation circuit as the research required a peak to peak ripple of 8V and 200mV for the EV - charger and telecom power supply, respectively.   A novel output passive ripple cancellation technique was developed for the EV charger case due to the ease it offers in terms of control, circuit complexity and extremely low THDi when compared with the active cancellation approach. The ripple circuit reduced the 50V ripple to 431mV with the use of a total of 2.2mF capacitance at the output stage.   Despite designing the passive technique, an active ripple cancellation circuit was designed using a buck converter circuit for the telecom power supply. The active approach was chosen because the passive has a slow response and incurs more loss at a high current level. Adding the active ripple cancellation circuit led to a quasi-single stage LLC PFC converter topology. A novel duty-ratio feedforward control was added to synchronize the PFC control of the input side with the buck topology ripple cancellation circuit. The addition of the ripple circuit with the feedforward control offered a peak to peak ripple of 6.7mV and a reduced resonant inductor current by half.   After analysis, an extremely low THDi of 0.47%, PF of 99.99% and a peak efficiency of 97.1% was obtained for the EV charger case. The telecom power supply offered a THDi of 2.3%, PF of 99.96% with a peak efficiency of 95%.