Wireless communication serves as the foundation for a wide range of services that have become an integral part of human life in this day and age. Driven by the desire to have a single piece of hardware that can provide multiple wireless services, attention has been directed to SDRs due to their programmable nature and the flexibility they can offer in operating over multiple standards. In addition, they can provide effective solutions to current challenges in wireless communication, such as spectrum overcrowding and inter-standard operability, as well as future challenges to come due to their upgradeability.
Although SDRs have been around in the research community for over a decade, they have not reached the point of transitioning to the mass consumer market, size being one of the major obstacles. Numerous SDR hardware platforms have been developed demonstrating successful functionality, yet to this day most of them remain trapped in desktop/benchtop form factors which are not suited for mobility. A main factor contributing to the size of SDR units is the RF front end. Using current technology, wide-band operation of SDR RF front-ends is achieved by aggregating multiple dedicated components, each covering a portion of the frequency range. Recent technology advances have enabled the integration of wide frequency functionality inside a single integrated package. One example is a prototype RFIC transceiver chip from Motorola Research Labs which contains a complete direct conversion RF transceiver in a single chip, with a frequency coverage range of 100MHz-2.4GHz. RFIC5, the latest version of the chip, has additionally integrated high speed ADC and DAC units, leading to a significant reduction in the component count and the overall size of the SDR hardware.
This thesis describes the implementation of a highly compact, SDR PC plug-in card, known as PicoRF. PicoRF is based on the Motorola's RFIC chip for the RF front-end functionality, while the combined computational power of a V5 FPGA and a PC host is used for waveform signal processing. An overlay gird consisting of an interconnection of PR slots is reserved on the FPGA to host the components of a signal processing pipeline which can be modified during run-time. Through a high speed PCIe connection, partial bitstreams can be downloaded from the host PC to the FPGA at a very high speed making it possible for the radio to modify its function in very short time intervals and greatly reducing the service interruption time. Control software running on the PC host manages the overall system operation including the RFIC which is controlled through a custom developed API. The combination of the laptop host and the plug-in card form a small form factor, mobile SDR node that is one step towards satisfying both the performance and ergonomics demand of the consumer market. / Master of Science
| Identifer | oai:union.ndltd.org:VTETD/oai:vtechworks.lib.vt.edu:10919/34443 |
| Date | 29 October 2012 |
| Creators | Said, Karim A. |
| Contributors | Electrical and Computer Engineering, Reed, Jeffrey H., Dietrich, Carl B., Athanas, Peter M. |
| Publisher | Virginia Tech |
| Source Sets | Virginia Tech Theses and Dissertation |
| Detected Language | English |
| Type | Thesis |
| Format | application/pdf |
| Rights | In Copyright, http://rightsstatements.org/vocab/InC/1.0/ |
| Relation | Said_Karim.A_T_2012_1.pdf |
Page generated in 0.0024 seconds