<p>In this thesis a prototype board for data aqcusition is designed and manufactured. The board is compliant with Compact PCI Express and it can sample an analog signal with two time interleaved ADC:s. Furthermore, the board is also equiped with one FPGA for the possibility of signal processing. The thesis also include a study for investigation what is needed for a total solution for data aqcusition, represention and managing the sampled data with LabView.</p>

In this thesis a prototype board for data aqcusition is designed and manufactured. The board is compliant with Compact PCI Express and it can sample an analog signal with two time interleaved ADC:s. Furthermore, the board is also equiped with one FPGA for the possibility of signal processing. The thesis also include a study for investigation what is needed for a total solution for data aqcusition, represention and managing the sampled data with LabView.

abstract: A new type of Ethernet switch based on the PCI Express switching fabric is being presented. The switch leverages PCI Express peer-to-peer communication protocol to implement high performance Ethernet packet switching. The advantages and challenges of using the PCI Express as the switching fabric are addressed. The PCI Express is a high-speed short-distance communication protocol largely used in motherboard-level interconnects. The total bandwidth of a PCI Express 3.0 link can reach as high as 256 gigabit per second (Gb/s) per 16 lanes. Concerns for PCI Express such as buffer speed, address mapping, Quality of Service and power consumption need to be considered. An overview of the proposed Ethernet switch architecture is presented. The switch consists of a PCI Express switching fabric and multiple adaptor cards. The thesis reviews the peer-to-peer (P2P) communication protocol used in the switching fabric. The thesis also discusses the packet routing procedure in P2P protocol in detail. The Ethernet switch utilizes a portion of the Quality of Service provided with PCI Express to ensure guaranteed transmission. The thesis presents a method of adapting Ethernet packets over the PCI Express transaction layer packets. The adaptor card is divided into the following two parts: receive path and transmit path. The commercial off-the-shelf Media Access Control (MAC) core and PCI Express endpoint core are used in the adaptor. The output address lookup logic block is responsible for converting Ethernet MAC addresses to PCI Express port addresses. Different methods of providing Quality of Service in the adaptor card include classification, flow control, and error detection with the cooperation of the PCI Express switch are discussed. The adaptor logic is implemented in Verilog hardware description language. Functional simulation is conducted in ModelSim. The simulation results show that the Ethernet packets are able to be converted to the corresponding PCI Express transaction layer packets based on their destination MAC addresses. The transaction layer packets are then converted back to Ethernet packets. A functionally correct FPGA logic of the adaptor card is ready for implementation on real FPGA development board. / Dissertation/Thesis / M.S. Electrical Engineering 2012

O foco central desse trabalho é a utilização e aprimoramento de um framework Peripheral Component Interconnect Express (PCI Express®) para a comunicação de dados em um Espectrômetro Digital de Ressonância Magnética (Digital Magnetic Resonance Spectrometer &#8211; DMRS) utilizando o conceito de Field-Programmable Gate Array (FPGA). Esse trabalho foi desenvolvido para servir como base de comunicação para o Espectrômetro Digital de Ressonância Magnética do Centro de Imagens e Espectroscopia in vivo por Ressonância Magnética (CIERMag) devido ao requerimento de altas taxas de transferência dos dados adquiridos. A integração dessa nova comunicação, entre o software e o hardware do espectrômetro, mantém compatibilidade com as interfaces já existentes possibilitando a execução de todas as sequências desenvolvidas sem nenhuma alteração. A incorporação da comunicação PCI Express provê uma solução com um número menor de etapas por transferência em comparação com a comunicação Ethernet. Com isso é possível aumentar o desempenho do sistema e obter taxas de transferência mais elevadas. Para isso, foram feitas mudanças no hardware de forma a torná-lo mais eficiente, reduzindo o número de ciclos de clock por operação e também a quantidade de lógica sintetizada. Além disso, a latência do software durante as transferências também foi reduzida através da utilização de interrupções Message Signaled Interrupt (MSI) e do método Scatter and Gather usado para reduzir a quantidade de cópias de dados na memória principal do computador. Dessa forma, obteve-se, como resultados reais, uma taxa de transferência efetiva (throughput) de 97% do valor máximo da banda possível do barramento PCI Express. / The central focus of this work is the implementation and use of a Peripheral Component Interconnect Express (PCI Express®) framework for data communication on a Digital Magnetic Resonance Spectrometer (DMRS) using the concept of Field-Programmable Gate Array (FPGA). This work is being developed to serve as a communication basis for the magnetic resonance Digital Spectrometer of the Centro de Imagens e Espectroscopia in vivo por Ressonância Magnética (CIERMag) due to demand of high transfer rates of acquired data. The integration of this new communication, between spectrometer software and hardware, keeps compatibility with existing interfaces, making it possible to execute all developed magnetic resonance sequences without any change. The incorporation of PCI Express communication provides solution with a lower number of steps per transfer when compared to Ethernet communication. By this means it\'s possible to increase system performance and, as result, have higher transfer rates. To accomplish that, the number of clock cycles per operation was reduced, so was the synthesized logic. Furthermore, software latency for data transfer was also reduced consequence of MSI interruption implementation and the use of Scatter and Gather method to remove data movement across the computer main memory. Therefore, it was obtained, as measured real result, a throughput value of 97% the theoretical maximum value for the hardware.

O foco central desse trabalho é a utilização e aprimoramento de um framework Peripheral Component Interconnect Express (PCI Express®) para a comunicação de dados em um Espectrômetro Digital de Ressonância Magnética (Digital Magnetic Resonance Spectrometer &#8211; DMRS) utilizando o conceito de Field-Programmable Gate Array (FPGA). Esse trabalho foi desenvolvido para servir como base de comunicação para o Espectrômetro Digital de Ressonância Magnética do Centro de Imagens e Espectroscopia in vivo por Ressonância Magnética (CIERMag) devido ao requerimento de altas taxas de transferência dos dados adquiridos. A integração dessa nova comunicação, entre o software e o hardware do espectrômetro, mantém compatibilidade com as interfaces já existentes possibilitando a execução de todas as sequências desenvolvidas sem nenhuma alteração. A incorporação da comunicação PCI Express provê uma solução com um número menor de etapas por transferência em comparação com a comunicação Ethernet. Com isso é possível aumentar o desempenho do sistema e obter taxas de transferência mais elevadas. Para isso, foram feitas mudanças no hardware de forma a torná-lo mais eficiente, reduzindo o número de ciclos de clock por operação e também a quantidade de lógica sintetizada. Além disso, a latência do software durante as transferências também foi reduzida através da utilização de interrupções Message Signaled Interrupt (MSI) e do método Scatter and Gather usado para reduzir a quantidade de cópias de dados na memória principal do computador. Dessa forma, obteve-se, como resultados reais, uma taxa de transferência efetiva (throughput) de 97% do valor máximo da banda possível do barramento PCI Express. / The central focus of this work is the implementation and use of a Peripheral Component Interconnect Express (PCI Express®) framework for data communication on a Digital Magnetic Resonance Spectrometer (DMRS) using the concept of Field-Programmable Gate Array (FPGA). This work is being developed to serve as a communication basis for the magnetic resonance Digital Spectrometer of the Centro de Imagens e Espectroscopia in vivo por Ressonância Magnética (CIERMag) due to demand of high transfer rates of acquired data. The integration of this new communication, between spectrometer software and hardware, keeps compatibility with existing interfaces, making it possible to execute all developed magnetic resonance sequences without any change. The incorporation of PCI Express communication provides solution with a lower number of steps per transfer when compared to Ethernet communication. By this means it\'s possible to increase system performance and, as result, have higher transfer rates. To accomplish that, the number of clock cycles per operation was reduced, so was the synthesized logic. Furthermore, software latency for data transfer was also reduced consequence of MSI interruption implementation and the use of Scatter and Gather method to remove data movement across the computer main memory. Therefore, it was obtained, as measured real result, a throughput value of 97% the theoretical maximum value for the hardware.

Partial reconfiguration (PR) is the process of configuring a subset of resources on a Field Programmable Gate Array (FPGA) while the remainder of the device continues to operate. PR extends the usability of FPGAs and makes it possible to perform design bootstrapping. Just like bootstrapping in PCs, bootstrapping in FPGAs consists of using a small application to initialize basic services and load a larger, more complex application to the device. Bootstrapping allows for unique design applications that can be used to maintain communication services, increase design security, reduce initial configuration time, and reduce nonvolatile configuration memory storage. This thesis presents a generic bootstrap framework that can be used to construct a variety of bootstrap designs. This thesis also discusses necessary PR design rules and techniques for bootstrap design creation. Additionally, this thesis presents two applications that demonstrate the feasibility of bootstrapping. One application is a bootstrap loader featuring a PCI Express endpoint; this loader is capable of reconfiguring a subset of the hardware on an as-need basis. The other application is a prototype designed to demonstrate the bootstrapping for nonvolatile configuration memory reduction in space-bound payloads. While bootstrap design is more complex than standard FPGA designs, bootstrapping increases the flexibility and capability of FPGAs.

Wireless communication serves as the foundation for a wide range of services that have become an integral part of human life in this day and age. Driven by the desire to have a single piece of hardware that can provide multiple wireless services, attention has been directed to SDRs due to their programmable nature and the flexibility they can offer in operating over multiple standards. In addition, they can provide effective solutions to current challenges in wireless communication, such as spectrum overcrowding and inter-standard operability, as well as future challenges to come due to their upgradeability. Although SDRs have been around in the research community for over a decade, they have not reached the point of transitioning to the mass consumer market, size being one of the major obstacles. Numerous SDR hardware platforms have been developed demonstrating successful functionality, yet to this day most of them remain trapped in desktop/benchtop form factors which are not suited for mobility. A main factor contributing to the size of SDR units is the RF front end. Using current technology, wide-band operation of SDR RF front-ends is achieved by aggregating multiple dedicated components, each covering a portion of the frequency range. Recent technology advances have enabled the integration of wide frequency functionality inside a single integrated package. One example is a prototype RFIC transceiver chip from Motorola Research Labs which contains a complete direct conversion RF transceiver in a single chip, with a frequency coverage range of 100MHz-2.4GHz. RFIC5, the latest version of the chip, has additionally integrated high speed ADC and DAC units, leading to a significant reduction in the component count and the overall size of the SDR hardware. This thesis describes the implementation of a highly compact, SDR PC plug-in card, known as PicoRF. PicoRF is based on the Motorola's RFIC chip for the RF front-end functionality, while the combined computational power of a V5 FPGA and a PC host is used for waveform signal processing. An overlay gird consisting of an interconnection of PR slots is reserved on the FPGA to host the components of a signal processing pipeline which can be modified during run-time. Through a high speed PCIe connection, partial bitstreams can be downloaded from the host PC to the FPGA at a very high speed making it possible for the radio to modify its function in very short time intervals and greatly reducing the service interruption time. Control software running on the PC host manages the overall system operation including the RFIC which is controlled through a custom developed API. The combination of the laptop host and the plug-in card form a small form factor, mobile SDR node that is one step towards satisfying both the performance and ergonomics demand of the consumer market. / Master of Science

L’objectif du projet, dont le travail présenté dans cette thèse est une partie, était de développer une caméra à rayons X ultra-rapide utilisant des pixels hybrides pour l’imagerie biomédicale et la science des matériaux. La technologie à pixels hybrides permet de répondre aux besoins des ces deux champs de recherche, en particulier en apportant la possibilité de sélectionner l’énergie des rayons X détectés et de les imager à faible dose. Dans cette thèse, nous présentons une caméra ultra-rapide basée sur l’utilisation de circuits intégrés XPAD3-S développés pour le comptage de rayons X. En collaboration avec l’ESRF et SOLEIL, le CPPM a construit trois caméras XPAD3. Deux d’entre elles sont utilisée sur les lignes de faisceau des synchrotrons SOLEIL et ESRF, et le troisième est installé dans le dispositif d’irradiation PIXSCAN II du CPPM. La caméra XPAD3 est un détecteur de rayons X de grande surface composé de huit modules de détection comprenant chacun sept circuits XPAD3-S équipés d’un système d’acquisition de données ultra-rapide. Le système de lecture de la caméra est basé sur l’interface PCI Express et sur l’utilisation de circuits programmables FPGA. La caméra permet d’obtenir jusqu’à 240 images/s, le nombre maximum d’images étant limité par la taille de la mémoire RAM du PC d’acquisition. Les performances de ce dispositif ont été caractérisées grâce à plusieurs expériences à haut débit de lecture réalisées dans le système d’irradiation PIXSCAN II. Celles-ci sont décrites dans le dernier chapitre de cette thèse. / The aim of the project, of which the work described in this thesis is part, was to design a high-speed X-ray camera using hybrid pixels applied to biomedical imaging and for material science. As a matter of fact the hybrid pixel technology meets the requirements of these two research fields, particularly by providing energy selection and low dose imaging capabilities. In this thesis, high frame rate X-ray imaging based on the XPAD3-S photons counting chip is presented. Within a collaboration between CPPM, ESRF and SOLEIL, three XPAD3 cameras were built. Two of them are being operated at the beamline of the ESRF and SOLEIL synchrotron facilities and the third one is embedded in the PIXSCAN II irradiation setup of CPPM. The XPAD3 camera is a large surface X-ray detector composed of eight detection modules of seven XPAD3-S chips each with a high-speed data acquisition system. The readout architecture of the camera is based on the PCI Express interface and on programmable FPGA chips. The camera achieves a readout speed of 240 images/s, with maximum number of images limited by the RAM memory of the acquisition PC. The performance of the device was characterize by carrying out several high speed imaging experiments using the PIXSCAN II irradiation setup described in the last chapter of this thesis.

ITC/USA 2009 Conference Proceedings / The Forty-Fifth Annual International Telemetering Conference and Technical Exhibition / October 26-29, 2009 / Riviera Hotel & Convention Center, Las Vegas, Nevada / Telemetry data recorders are not immune to the effects that a number of disruptive technologies have had on the telemetry industry. Data recorder designs today make use of data buses, storage types and graphical user interfaces that are constantly evolving based on the advances of personal computer and consumer electronics technologies. Many of these recorders use embedded designs that integrate disruptive technologies such as PCI Express for realtime data and signal processing, SATA interfaces for data storage and touchscreen technologies to provide an intuitive operator interface. Solid state drives also play a larger role in the latest recorder designs. This paper will explore the effects of these technologies on the latest telemetry recorders in terms of the benefits to the users, cost of implementation, obsolescence management, and integration considerations. The implications of early adoption of disruptive technologies will also be reviewed.

Reconfigurable devices are the mainstream in today’s system on chip solutions. Reconfigurable devices have the advantages of reduced cost over their equivalent custom design, quick time to market and the ability to reconfigure the design at will and ease. One such reconfigurable device is an FPGA. In this industrial thesis, the design and implementation of a control process interface using ECP2M FPGA and PCIe communication is accomplished. This control process interface is designed and implemented for a 3-D plotter system called LSC11. In this thesis, the FPGA unit implemented drives the plotter device based on specific timing requirements charted by the customer. The FPGA unit is interfaced to a Host CPU in this thesis (through PCIe communication) for controlling the LSC11 system using a custom software. All the peripherals required for the LSC11 system such as the ADC, DAC, Quadrature decoder and the PWM unit are also implemented as part of this thesis. This thesis also implements an efficient methodology to send all the inputs of the LSC11 system to the Host CPU without the necessity for issuing any cyclic read commands on the Host CPU. The RTL design is synthesised in FPGA and the system is verified for correctness and accuracy. The LSC11 system design consumed 79% of the total FPGA resources and the maximum clock frequency achieved was 130 Mhz. This thesis has been carried out at Abaxor Engineering GmbH, Germany. It is demonstrated in this thesis how FPGA aids in quick designing and implementation of system on chip solutions with PCIe communication.