In this work, a simplified method for performing characterization of a standard cell is presented. The method presented here is based on Synopsys models of cell delay and power dissipation, in particular the linear delay model. This model is chosen as it allows rapid characterization with a modest number of simulations, while still achieving acceptable accuracy. Additionally, a guideline for developing standard cell libraries for use with Synopsys synthesis and simulation tools and Cadence Placement-and-Routing tools is presented. A cell layout library, built in accordance with the presented guidelines, was laid out, and a test chip, namely a dual 4-bit counter, was built using the library to demonstrate the suitability of the method. / Master of Science
| Identifer | oai:union.ndltd.org:VTETD/oai:vtechworks.lib.vt.edu:10919/34842 |
| Date | 01 September 2000 |
| Creators | Sulistyo, Jos Budi |
| Contributors | Electrical and Computer Engineering, Ha, Dong Sam, Armstrong, James R., Gray, Festus Gail |
| Publisher | Virginia Tech |
| Source Sets | Virginia Tech Theses and Dissertation |
| Detected Language | English |
| Type | Thesis |
| Format | application/pdf |
| Rights | In Copyright, http://rightsstatements.org/vocab/InC/1.0/ |
| Relation | thesis.pdf |
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