Application Specific Integrated Circuits (ASICs) are critical to delivering on 5G’s promises of high speed, low latency, and expanded capacity. Digital Front-End (DFE) ASICs are particularly important components because they enhance crucial signal processing activities. It handles duties including carrier mixing, up-sampling, and modulation-demodulation, allowing for efficient data transmission and reception inthe complicated 5G environment. The main aim of this work is to develop a power estimation tool for DFE radio ASICs and to understand the different use cases. It also studies the spread of power consumption, taking into account process and metal variations. The thesis provides a detailed case study of the DFE ASIC, including its Intellectual Property (IP) blocks, configurations, and protocols. It investigates the power consumption of DFE ASICs under various conditions, including active processing, power-saving mode, and no clock. In this thesis we build a power model that describes how the factors affect the ASIC’s power consumption. It also performs spread analysis to evaluate the impact of all factors using MATLAB tool. Based on this we then generate three distributionmodels to study the combined likelihood of the variations. It also uses Monte Carlo simulation to understand total power usage. Through this work we can conclude that the power consumption of DFE ASICs is affected by a variety of factors. The power model and spread analysis can be usedto forecast and optimize power usage in 5G systems.
| Identifer | oai:union.ndltd.org:UPSALLA1/oai:DiVA.org:bth-25545 |
| Date | January 2023 |
| Creators | Bhutada, Rajnandini |
| Publisher | Blekinge Tekniska Högskola, Institutionen för datavetenskap |
| Source Sets | DiVA Archive at Upsalla University |
| Language | English |
| Detected Language | English |
| Type | Student thesis, info:eu-repo/semantics/bachelorThesis, text |
| Format | application/pdf |
| Rights | info:eu-repo/semantics/openAccess |
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