In this thesis, we propose a novel vertical MOSFET device with middle partial insulator (MPI) or VMPI for capacitorless one transistor dynamic random access memory (1T-DRAM) application. In TCAD simulations, we compare the device performances of the planar MPI, conventional silicon-on-insulator SOI, and our proposed VMPI. Based on numerical simulation, we find out that the VMPI device has a large kink phenomenon for improving the programming window. As far as the data retention time is concerned, the hole carriers leaking into the source region are reduced due to the presence of a large pseudo neutral region and an effective blocking oxide layer. The retention time can thus be improved about 5 times when compared with conventional SOI counterpart. Furthermore, it should be noted that the gate-all-around (GAA) VMPI device structure not only increases the body pseudo-neutral region, but also enhances the 1T-DRAM performances, suggesting that the proposed VMPI can become a candidate for 1T-DRAM application.
| Identifer | oai:union.ndltd.org:NSYSU/oai:NSYSU:etd-0803111-152307 |
| Date | 03 August 2011 |
| Creators | Chen, Cheng-Hsin |
| Contributors | Chee-Wee Liu, Jyi-Tsong Lin, Chun-Hsing Shih, Wen-Kuan Yeh, Feng-Der Chin |
| Publisher | NSYSU |
| Source Sets | NSYSU Electronic Thesis and Dissertation Archive |
| Language | Cholon |
| Detected Language | English |
| Type | text |
| Format | application/pdf |
| Source | http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0803111-152307 |
| Rights | user_define, Copyright information available at source archive |
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