SAR-ADCs are very popular and suitable for conversions up to few tens of MHz with 8 to 12 bits of resolution. A very popular type is the Charge Redistribution SAR-ADC which is based on a capacitive array. Higher speeds can be achieved by using the interleaving technique where a number of SAR-ADCs are working in parallel. These speeds, however, can only be achieved if the reference voltage can cope with the switching of the capacitive array. In this thesis the design of a programmable voltage reference generator for a Charge Redistribution SAR-ADC was studied. A number of architectures were studied and one based on a Current Steering DAC was chosen because of the settling time that could offer to the Charge Redistribution SAR-ADC switching operation. This architecture was further investigated in order to spot the weak points of the design and try to minimize the settling time. In the end, the final design was evaluated and possible trimming techniques were proposed that could further speed up the design.
| Identifer | oai:union.ndltd.org:UPSALLA1/oai:DiVA.org:liu-98567 |
| Date | January 2013 |
| Creators | Mylonas, Georgios |
| Publisher | Linköpings universitet, Elektroniksystem, Linköpings universitet, Tekniska högskolan |
| Source Sets | DiVA Archive at Upsalla University |
| Language | English |
| Detected Language | English |
| Type | Student thesis, info:eu-repo/semantics/bachelorThesis, text |
| Format | application/pdf |
| Rights | info:eu-repo/semantics/openAccess |
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