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A Design Study of an Arithmetic Unit for Finite Fields / En Designstudie av en Aritmetisk Enhet för Ändliga Kroppar

<p>This thesis investigates how systolic architectures can be used in the implementation of an arithmetic unit for small finite fields of characteristic two with polynomial basis representation. </p><p>Systolic architectures provide very high performance but also consume a lot of chip area. A number of design methods for tailoring the systolic arrays for a specified requirement are presented, making it possible to trade throughput, chip area and propagation delays for oneanother. </p><p>A study is also made on how these systolic arrays can be combined to form an arithmetic logic unit, ALU, that canperform operations in many different fields. A number of design alternatives are presented, and an example ALU is presented to give an idea of the performance of such a circuit.</p>

Identiferoai:union.ndltd.org:UPSALLA/oai:DiVA.org:liu-1799
Date January 2003
CreatorsTångring, Ivar
PublisherLinköping University, Department of Electrical Engineering, Institutionen för systemteknik
Source SetsDiVA Archive at Upsalla University
LanguageEnglish
Detected LanguageEnglish
TypeStudent thesis, text
RelationLiTH-ISY-Ex, ; 3396

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