This study investigated the Class-E power amplifier operating at 5.2 GHz. Since the operation of this amplifier applies a lot of stress on the switching transistor, a cascode topology was applied in order to reduce the drain-source voltage stress. Such an amplifier was designed and optimized in order to improve stability, power added efficiency, and matching. A layout for the said design was then created to be fabrication-ready using the TSMC 0.18 um technology. Post-layout simulations were performed in order to realize a more realistic circuit performance with the layout design in mind. Long-term stress effects, such as oxide breakdown, on the key transistors were modeled and simulated in order to achieve an understanding of how leakage currents affect the overall circuit performance. Simulated results were compared and contrasted against theoretical understanding using derived equations. Recommendations for future advancements were made for modification and optimization of the circuit by the application of other stress reduction strategies, variation in the class-E topology, and improvement of the driver stage.
| Identifer | oai:union.ndltd.org:ucf.edu/oai:stars.library.ucf.edu:etd-5445 |
| Date | 01 January 2010 |
| Creators | Kutty, Karan |
| Publisher | STARS |
| Source Sets | University of Central Florida |
| Language | English |
| Detected Language | English |
| Type | text |
| Format | application/pdf |
| Source | Electronic Theses and Dissertations |
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