Ethylene propylene rubber (EPR) cable has been extensively used for distribution of power. The insulation of cable should withstand electrical, thermal, mechanical, and chemical stresses during its operation. It is imperative to measure the data providing dielectric strength of EPR cable for these stresses. Significant improvements on the quality of insulation have been progressing for better performance of cable under these stresses. This study deals with ac voltage stress imposed on the cable. The electrical breakdown strength of 5kV EPR cable under ac voltage has been measured by constructing a suitable test set in Mississippi State University High Voltage Lab.

abstract: Infant mortality rate of field deployed photovoltaic (PV) modules may be expected to be higher than that estimated by standard qualification tests. The reason for increased failure rates may be attributed to the high system voltages. High voltages (HV) in grid connected modules induce additional stress factors that cause new degradation mechanisms. These new degradation mechanisms are not recognized by qualification stress tests. To study and model the effect of high system voltages, recently, potential induced degradation (PID) test method has been introduced. Using PID studies, it has been reported that high voltage failure rates are essentially due to increased leakage currents from active semiconducting layer to the grounded module frame, through encapsulant and/or glass. This project involved designing and commissioning of a new PID test bed at Photovoltaic Reliability Laboratory (PRL) of Arizona State University (ASU) to study the mechanisms of HV induced degradation. In this study, PID stress tests have been performed on accelerated stress modules, in addition to fresh modules of crystalline silicon technology. Accelerated stressing includes thermal cycling (TC200 cycles) and damp heat (1000 hours) tests as per IEC 61215. Failure rates in field deployed modules that are exposed to long term weather conditions are better simulated by conducting HV tests on prior accelerated stress tested modules. The PID testing was performed in 3 phases on a set of 5 mono crystalline silicon modules. In Phase-I of PID test, a positive bias of +600 V was applied, between shorted leads and frame of each module, on 3 modules with conducting carbon coating on glass superstrate. The 3 module set was comprised of: 1 fresh control, TC200 and DH1000. The PID test was conducted in an environmental chamber by stressing the modules at 85°C, for 35 hours with an intermittent evaluation for Arrhenius effects. In the Phase-II, a negative bias of -600 V was applied on a set of 3 modules in the chamber as defined above. The 3 module set in phase-II was comprised of: control module from phase-I, TC200 and DH1000. In the Phase-III, the same set of 3 modules which were used in the phase-II again subjected to +600 V bias to observe the recovery of lost power during the Phase-II. Electrical performance, infrared (IR) and electroluminescence (EL) were done prior and post PID testing. It was observed that high voltage positive bias in the first phase resulted in little/no power loss, high voltage negative bias in the second phase caused significant power loss and the high voltage positive bias in the third phase resulted in major recovery of lost power. / Dissertation/Thesis / M.S. Engineering 2011

Les mémoires résistives ReRAM (ou memristors) sont destinées à remplacer les mémoires non volatiles Flash. Les ReRAM utilisent le changement de résistance d’une structure MIM (Métal-Isolant-Métal) soumise à un stress en tension. Jusqu’à présent, l’attention était focalisée sur les mécanismes qui régissent la commutation de résistance dans les dispositifs ReRAM. Moins d’attention a été accordée à la variation de capacitance, c'est-à-dire à la variation de capacité des structures MIM lorsque ces dernières sont soumises à un stress en tension. C’est sur ce dernier point que notre travail porte. Nous étudions la variation d’impédance (conductance et capacitance dans le domaine RF) dans des structures MIM à base de HfO2. Au-delà d’une tension seuil (Set) une diminution de la capacitance est observée, conjointement à une augmentation de conductance. Des cycles mémoires capacité-tension (C-V) et conductance-tension (G-V) sont obtenus de manière reproductible. Des caractérisations en fréquence (C-f et G-f), sous différentes polarisations continues, sont effectuées pour mieux comprendre les mécanismes de commutation de l’impédance. La diminution de capacitance dans l’état conducteur (ON) est attribuée au caractère inductif des filaments conducteurs formés pendant l’étape de Set. Les mécanismes de transport conduisant à l’apparition de ce caractère inductif sont discutés. Nous montrons également l’influence du procédé de dépôt (ALD) de HfO2 sur les caractéristiques C-V et G-V, ainsi que les modifications apportées par l’emploi d’une structure bicouche. Ce travail ouvre la voie à la réalisation de dispositifs à mémoire de capacitance (mem-capacitors), et plus généralement de composants à mémoire d’impédance (ZRAM). Le potentiel de ces dispositifs pour réaliser un filtre reconfigurable (programmable en tension) est démontré d’une manière pratique. / Resistive random access memories (ReRAM) hold great potential for replacing Flash memories. A ReRAM memory (or MEMRISTOR) uses a resistive switching phenomenon found in Metal-Insulator-Metal (MIM) structures under a voltage stress. Most researches were focused on the mechanisms governing the resistance switching in ReRAM devices and less attention has been paid to capacitance variation of MIM structures under a voltage stress. Our work is focused on that latter phenomenon. We study impedance variation (conductance and capacitance in the RF domain) in HfO2-based MIM structures. Above a threshold voltage (Set), concurrently to conductance increase, a decrease in the capacitance value is observed. Reproducible capacitance-voltage (C-V) and conductance-voltage (G-V) memory cycles are obtained. Frequency dependent characterizations (C-f and G-f), under different DC bias voltages, are performed with the aim of understanding the mechanisms of impedance switching. The capacitance decrease observed in the conducting (ON) state is attributed to the inductance of the filament created during the Set stage. Transport phenomena responsible for the filament inductive behavior are discussed. Impact of HfO2 deposition process (ALD), as well as the use of bi-layer structures, on C-V and G-V characteristics are shown. This work paves the way for the realization of new capacitance memory devices (mem-capacitors) and most generally for impedance memories (ZRAM). Potential of these devices to design reconfigurable filters (controlled by voltage bias) is demonstrated in a practical way.

This study investigated the Class-E power amplifier operating at 5.2 GHz. Since the operation of this amplifier applies a lot of stress on the switching transistor, a cascode topology was applied in order to reduce the drain-source voltage stress. Such an amplifier was designed and optimized in order to improve stability, power added efficiency, and matching. A layout for the said design was then created to be fabrication-ready using the TSMC 0.18 um technology. Post-layout simulations were performed in order to realize a more realistic circuit performance with the layout design in mind. Long-term stress effects, such as oxide breakdown, on the key transistors were modeled and simulated in order to achieve an understanding of how leakage currents affect the overall circuit performance. Simulated results were compared and contrasted against theoretical understanding using derived equations. Recommendations for future advancements were made for modification and optimization of the circuit by the application of other stress reduction strategies, variation in the class-E topology, and improvement of the driver stage.

Tato disertační práce se věnuje studiu částečných výbojů (PD) způsobených poklesem spolehlivosti a životnosti elektronických zařízení a systémů. Diagnostika PD je dnes známá metoda pro vysoké napětí u vysoko-výkonných zařízení. V případě elektronických zařízení PD testování není ale běžně používáná metoda, přestože je zde také potenciál pro vysoké elektrické zatížení vzhledem k velmi krátké vzdálenosti. Tato práce je zaměřena na vyšetřování PD činnosti u elektronických zařízení. Bylo navrženo a provedeno pracoviště pro diagnostiku PD v elektronických zařízeních. Pracovní frekvence se pohybuje od několika stovek Hz až 100 kHz. Maximální amplituda PD testovaného napětí je vyšší než 10 kV. Navzdory jednoduché konstrukci toto zařízení přináší vysokou spolehlivost měření. Více než 300 PD testů bylo provedeno na různých elektronických zařízeních a elektronických součástí,např. na planárních transformátorech a elektronických komponentách používaných při vysoko-napěťových měničích

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This thesis describes the flexible voltage control of a multi-level-voltage-reinjection voltage source converter. The main purposes are to achieve reactive power generation flexibility when applied for HVdc transmission systems, reduce dynamic voltage balancing for direct series connected switches and an improvement of high power converter efficiency and reliability. Waveform shapes and the impact on ac harmonics caused by the modulation process are studied in detail. A configuration is proposed embracing concepts of multi level, soft-switching and harmonic cancellation. For the configuration, the firing sequence, waveform analysis, steady-state and dynamic performances and close-loop control strategies are presented. In order not to severely compromise the original advantages of the converter, the modulated waveforms are proposed based on the restrictions imposed mathematically by the harmonic cancellation concept and practically by the synthesis circuit complexity and high switching losses. The harmonic impact on the ac power system prompted by the modulation process is studied from idealistic and practical aspects. The circuit topology being proposed in this thesis is developed from a 12-pulse bridge and a converter used classically for inverting power from separated dc sources. Switching functions are deduced and current paths through the converter are analysed. Safe and steady-state operating regions of the converter are studied in phasor diagrams to facilitate the design of simple controllers for active power transfer and reactive power generations. An investigation into the application of this topology to the back-to-back VSC HVdc interconnection is preformed via EMTDC simulations.