Las topologías de convertidores multinivel han recibido una atención especial durante las dos últimas décadas debido a sus notables ventajas en aplicaciones de alta potencia y media/alta tensión. En estas topologías, y comparadas con el convertidor tradicional de dos niveles, el voltaje que soporta cada dispositivo semiconductor es menor, evitando los problemas asociados con la interconexión serie de dispositivos. La distorsión armónica en la tensión de salida es también menor y la eficiencia mayor. Pero incorporan un número superior de dispositivos semiconductores y la estrategia de modulación resultante es, por tanto, más compleja.Entre estas topologías, el convertidor cc-ca de tres niveles trifásico con conexión al punto neutro del bus de cc es probablemente el más popular. La aplicación a este convertidor de técnicas de modulación convencionales causa una oscilación de la tensión del punto neutro de baja frecuencia (tres veces la frecuencia fundamental de la tensión de salida). Esta oscilación, a su vez, supone un incremento del estrés de tensión de los dispositivos y provoca la aparición de armónicos de baja frecuencia en la tensión de salida.Esta tesis presenta una nueva técnica de modulación del pulso de conducción de los dispositivos semiconductores para convertidores de tres niveles trifásicos con conexión a punto neutro, capaz de conseguir un control completo de la tensión del punto neutro con una distorsión armónica reducida en la tensión de salida alrededor de la frecuencia de conmutación. Esta nueva técnica de modulación, basada en la definición de unos vectores espaciales virtuales, garantiza el equilibrado de la tensión del punto neutro con cualquier carga (lineal o no, cualquier factor de potencia) y para todo el rango de tensión de salida, con el único requisito de que la suma de corrientes de fase sea nula.Las características de la técnica de modulación propuesta y sus beneficios con respecto a otras modulaciones se han verificado a través de simulaciones y experimentos tanto en lazo abierto como en lazo cerrado. / Multilevel converter topologies have received special attention during the last two decades due to their significant advantages in high-power medium- and high-voltage applications. In these topologies, and compared to the previous two-level case, the voltage across each semiconductor is reduced, avoiding the problems of the series interconnection of devices. The harmonic distortion of the output voltage is also diminished and the converter efficiency increases. But a larger number of semiconductors is needed and the modulation strategy to control them becomes more complex.Among these topologies, the three-level three-phase neutral-point-clamped voltage source inverter is probably the most popular. The application of traditional modulation techniques to this converter causes a low frequency (three times the fundamental frequency of the output voltage) oscillation of the neutral-point voltage. This, in turn, increases the voltage stress on the devices and generates low-order harmonics in the output voltage.This thesis presents a novel pulsewidth modulation for the three-level three-phase neutral-point-clamped converter, able to achieve a complete control of the neutral-point voltage while also having a low output voltage distortion at around the switching frequency. The new modulation, based on a virtual space vector concept, guarantees the balancing of the neutral-point voltage for any load (linear or nonlinear, any load power factor) over the full range of converter output voltage, the only requirement being that the addition of the output three-phase currents equals zero.The performance of this modulation approach and its benefits over other previously proposed solutions are verified through simulation and experiments in both open- and closed-loop converter configurations.

Coordenação de Aperfeiçoamento de Pessoal de Nível Superior / This dissertation deals with modulation techniques for multilevel diode clamped converters. The major challenge to be overcome by modulation strategies to these converters is the balance of the dc-link voltage capacitors, whilst minimizing the THD of output voltages. Among the modulation strategies reported in literature for this purpose are the carrier-based and space vector modulation techniques. Generally the space vetor methods select the nearest three vector to implement the desired output voltage vector. However, it is not always possible to remove the low frequency ripple in the dc-link voltage capacitors using this diagram vector. This work proposes a new space vector diagram that allows the elimination of the low frequency ripple in the dc-link voltage capacitors and guarantees the balance to the entire converter linear operation region, operating with any power factor load. Further constrains are derived based on the sign and magnitude of the output currents to determine the transition between the space vector diagram N3V and NS3V, making a hybrid modulation. As a result is possible to minimize the total harmonic distortion of the output voltages and to ensure the control of the averaged neutral point current. In order to make it possible to extend the results for converters with any number of levels, a carrier based modulation was proposed in this work where the modulation signals are chosen to ensure maximum use of the dc-link of the linear range of operation of converter, and eliminate low-frequency oscillation in the voltage capacitors. Moreover, it is proposed a space vector modulation strategy to back-to-back three level diode clamped converters, with the purpose to connect the wind power generation to the grid. This technique combines the utilization of the N3V and NS3V space vector diagrams for both converters connected to the same dc-link. Thus it is possible to establish a trade off between oscillation in the voltage capacitors and THD of output voltages. Experimental results and benchmarks are presented and demonstrate the good performance of the proposed methods. / Esta dissertação de mestrado trata de estratégias de modulação para conversores multiníveis com diodos de grampeamento. O principal desafio a ser superado por técnicas de modulação aplicadas a estes conversores é o de equilibrar as tensões dos capacitores do barramento CC, enquanto que minimizando a penalização da THD das tensões de saída. Dentre as principais estratégias de modulação com esse propósito abordadas na literatura, são as estratégias baseadas na comparação com portadora e as estratégias vetoriais. Geralmente os métodos de modulação vetorial utilizam os três vetores de comutação mais próximos do vetor de tensão de referência, N3V. Entretanto nem sempre é possível eliminar as ondulações de baixa frequência presentes nas tensões dos capacitores do barramento CC em toda faixa de operação do conversor utilizando essa divisão de setores. Este trabalho deriva um novo diagrama vetorial NS3V, que possibilita a eliminação das ondulações de baixa frequência das tensões dos capacitores do barramento CC na região linear do conversor, independente do fator de potência de operação. Além disso são obtidas restrições baseadas no sinal e nas magnitudes das correntes de saída para determinar a transição entre a modulação que utiliza o diagrama vetorial N3V e o diagrama vetorial NS3V, tornando a modulação híbrida. Com isto é possível minimizar a distorção harmônica das tensões de saída e assegurar o controle da corrente média sobre um período de comutação no ponto central do divisor capacitivo. Com objetivo de facilitar a extensão dos resultados para um número qualquer de níveis, a modulação baseada na comparação com portadora foi proposta nesse trabalho onde as tensões modulantes são escolhidas de forma a garantir a máxima utilização da tensão do barramento CC na faixa linear de operação do conversor, bem como eliminar as ondulações de baixa frequência presentes nas tensões dos capacitores. Ainda, é proposta uma estratégia de modulação vetorial para conversores com diodos de grampeamento de três níveis em configuração back-toback com o propósito de conectar sistemas de geração eólica à rede. Nesta estratégia de modulação é combinada a utilização dos diagramas vetoriais N3V e NS3V para ambos os conversores conectados ao mesmo barramento CC. Dessa forma é possível estabelecer um compromisso entre ondulação das tensões dos capacitores do barramento CC e THD das tensões de saída. Resultados experimentais e análises comparativas são apresentadas e demonstram a boa performance dos métodos propostos.

Three-level diode-clamped inverter is being widely used these days. Extensive research has been carried out on pulse width modulation (PWM) strategies for a three-level inverter. The most widely used PWM strategies are sine-triangle pulse width modulation (SPWM) and centered space vector pulse width modulation (CSVPWM). The influence of these PWM strategies on the DC-link capacitor current and voltage ripple is studied in this thesis. The sizing of the DC capacitor depends on value of the maximum RMS current flowing through it. In this work, an analytical expression for capacitor RMS current is derived as a function of operating conditions like modulation index, power factor angle of the load and peak load current. The worst case current stress on the capacitor is evaluated using the analytical expression. The capacitor RMS current is found to be the same in SPWM and CSVPWM schemes. The analytical expression is validated through simulations and experiments on a 3kVA MOSFET based three-level inverter. Harmonic analysis of the capacitor current is helpful in better evaluation of capacitor power loss. Therefore, harmonic analysis of the capacitor current is carried out, using the techniques of geometric wall model and double Fourier integral for SPWM and CSVPWM schemes. The theoretical predictions are validated through experiments. The capacitor RMS current is divided into low-frequency RMS current (where low frequency component is defined as a component whose frequency is less than half the switching frequency) and high-frequency RMS current. The capacitor voltage ripple is estimated analytically for SPWM and CSVPWM schemes, using the low-frequency and high-frequency capacitor RMS current. The voltage ripples due to SPWM and CSVPWM schemes are compared. It is found that the voltage ripple with SPWM is higher than that with CSVPWM. A simplified method to estimate the capacitor power loss, without the requirement of FFT analysis of capacitor current, is proposed. The results from this simplified method agree reasonably well with the results from the detailed method. A space vector based modulation scheme is proposed, which reduces the capacitor RMS current at high power factor angles. However, the proposed method leads to higher total harmonic distortion (THD) than CSVPWM. Simulation and experimental results, comparing CSVPWM and the proposed PWM, are presented.

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This thesis describes the flexible voltage control of a multi-level-voltage-reinjection voltage source converter. The main purposes are to achieve reactive power generation flexibility when applied for HVdc transmission systems, reduce dynamic voltage balancing for direct series connected switches and an improvement of high power converter efficiency and reliability. Waveform shapes and the impact on ac harmonics caused by the modulation process are studied in detail. A configuration is proposed embracing concepts of multi level, soft-switching and harmonic cancellation. For the configuration, the firing sequence, waveform analysis, steady-state and dynamic performances and close-loop control strategies are presented. In order not to severely compromise the original advantages of the converter, the modulated waveforms are proposed based on the restrictions imposed mathematically by the harmonic cancellation concept and practically by the synthesis circuit complexity and high switching losses. The harmonic impact on the ac power system prompted by the modulation process is studied from idealistic and practical aspects. The circuit topology being proposed in this thesis is developed from a 12-pulse bridge and a converter used classically for inverting power from separated dc sources. Switching functions are deduced and current paths through the converter are analysed. Safe and steady-state operating regions of the converter are studied in phasor diagrams to facilitate the design of simple controllers for active power transfer and reactive power generations. An investigation into the application of this topology to the back-to-back VSC HVdc interconnection is preformed via EMTDC simulations.

Use of multilevel inverters are inevitable in medium and high voltage drives. This is due to the fact that the multilevel inverters can produce voltages in smaller steps which will reduce the harmonic content and result in more sinusoidal voltages and currents as compared to voltages and currents from two-level inverters. Due to the device limitations, use of two-level inverters is not possible in medium and high voltage drive applications. Though multiple devices can be connected both in series and parallel to achieve two-level operation, the output voltages still suffer from high harmonic content. Multilevel inverters have multiple DC voltage levels with switches that enable one of the voltage steps to be applied to the load. Due to decrease in step size during each switching instant, output voltages and currents of the multilevel inverters have considerably less harmonic content. As the number of levels increase, the switching step reduces thereby the harmonic content also reduces drastically. Due to their advantages, multilevel inverters have gained lot of acceptance in the industry even at lower voltages. The three main configurations that have gained popularity are the neutral point clamped converter, the flying capacitor converter and the cascaded H-bridge converter. Each converter has its own set of advantages and disadvantages. Based on the requirements of various applications, it is possible to fabricate hybrid multilevel topologies that are combinations of the three basic topologies. Researchers around the world have proposed several such converters for diverse applications so as to suit particular requirements like modularity, ease of control, improved reliability, fault tolerant capability etc. The present thesis explores multilevel converters with single DC link to be used for motor drive and grid connected applications. A novel five-level inverter topology formed by cascading a floating capacitor H-bridge module to a regular three-level flying capacitor inverter has been explored in chapter 2. The three-level flying capacitor inverter can generate pole voltages of 0, VDC /2 and VDC . By cascading it with another floating capacitor H-bridge of voltage magnitude VDC /4, pole voltages of 0, VDC /4, VDC/2, 3VDC /4 and VDC . Each of these pole voltage levels can have one or more switching combinations. However each switching combination has a unique effect on the state of the two capacitor voltages. By switching through redundant switching combinations for the same pole voltage, the two capacitors present in each phase can be balanced. The proposed topology also has an advantage that if one of the devices in the H-bridge fails, the topology can still be operated as a regular three-level flying capacitor inverter that can supply full load at rated power by bypassing the faulty H-bridge. This fault tolerant operation of the converter will enable it to be used in applications like traction and marine drives where high reliability is needed. The proposed converter needs a single DC link. All the required voltage levels can be generated from the single DC link. This enables back to back grid connected operation possible where multiple converters can interact with a single DC link. Various pole voltage switching combination and its effect on individual capacitor has been studied. A control algorithm to balance the capacitor voltages by switching through multiple redundancies for the same pole voltage has been developed. The proposed configuration has been implemented in hardware using IGBT H-bridge modules and the control circuitry is realized using DSP and FPGA. The performance of the drive is verified for various frequencies and modulation indices during steady state by running a three phase induction motor at no load. The stability of the drive during transients has been studied by accelerating the machine suddenly at no load and analyzing the performance of the drive. The capacitor voltages are made to deviate from their intended values and the capacitor balancing algorithm has been verified for its ability to bring the capacitor voltages back to their intended values. The experimental results have been presented and discussed in detail in the chapter 2. In the third chapter a common-mode voltage eliminated three-level inverter using a single DC link has been proposed. The power schematic is similar to the one presented in chapter 2. In this chapter the space vector polygon formed by the three phases of the proposed topology has been presented. The common-mode voltage generated by different pole voltage combinations for same space vector location and the redundant switching state combinations has been studied. The pole voltage combinations with zero common mode voltage have been studied. The switching state redundancies for the the pole voltage have been studied. The space vector polygon formed with the pole voltage combinations has been analyzed. A drive is made with the proposed common-mode voltage eliminated inverter. The performance of the drive is tested for various modulation indices and frequencies by running a three phase squirrel cage induction motor at no load. The transient performance is verified by accelerating the motor suddenly and checking the common-mode voltage along with the capacitor voltages. The results have been presented and discussed in detail in chapter 3. This converter has advantages like use of single DC supply, ability to operate as a regular three level converter in case of failure of one of the H-bridges. The work presented in fourth chapter proposes a novel three phase 17-level inverter configuration which utilizes a single DC supply. The rest of voltages are generated using three floating capacitor H-bridges. The redundant switching combinations for generating various pole voltages and their effect on the capacitors have been studied and suitable capacitor balancing algorithm has been developed. The proposed topology has been realized in hardware and the performance of the drive during steady state has been studied by running an induction motor at various modulation indices and frequencies. The transient response of the drive has been observed by accelerating the motor suddenly under no load. The results have been presented in detail in chapter four. This configuration also needs a single DC link. The advantages of this configuration is in case of failure of any devices in the H-bridge, the drive can be operated at reduced number of levels while supplying full load current. This feature helps the drive to be used in fault tolerant applications like marine and traction drives where reliability of the drive is of prime importance. All the topologies that have been presented in the previous chapters have mentioned about the usage of the proposed genre of topologies use single DC link and hence will enable back to back grid tied inverter connection. In the fifth chapter this has has been verified experimentally. The three phase squirrel cage induction motor is driven by using the seventeen-level inverter drive proposed in chapter four. A five-level active front-end is realized by the converter topology proposed in chapter two. The converter is run and the performance of the drive is studied at various modulation indices and speeds of the motor. Various aspects like re-generation operation, acceleration and other aspects of the drive have been studied experimentally and the results are presented in detail. For experimental setup, Semikron SKM75GB12T4 IGBT modules have been used to realize the power topology. These IGBTs are driven by M56972L drivers. The control circuit is realized using TMS320F2812 DSP along with Xilinx Spartan 3 FPGA (XC3S200) has been used. The voltages and currents are sensed using LEM LV-20P and LA 55-P hall effect based sensors.