Graduation date: 2006 / The design of a 10-bit pipelined charge redistribution DAC employing MOSCAPs biased in their accumulation mode is presented in this thesis. A switched capacitor filter and output buffer have also been designed for the system. The effect of MOSCAP nonlinearity on the performance of the pipelined charge redistribution DAC has been analyzed. MOS capacitors and their models available for simulation have been discussed. In addition, the effect of more general capacitor nonlinearities on the performance of the DAC has been presented.
| Identifer | oai:union.ndltd.org:ORGSU/oai:ir.library.oregonstate.edu:1957/465 |
| Date | 21 September 2005 |
| Creators | Behera, Prachee Shree |
| Contributors | Temes, Gabor C, Settaluri, Raghu, Traylor, Roger, Kimura, Shoichi |
| Source Sets | Oregon State University |
| Language | en_US |
| Detected Language | English |
| Type | Thesis |
| Format | 1260770 bytes, application/pdf |
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