This thesis includes two topics. The first one is the architecture as well as the circuit implementation of an ultra low-power direct digital frequency synthesizer (DDFS) based on the straight line approximation. The second one is the circuit implementation of the low-power DDFS with an error compensation.
The proposed approximation technique replaces the conventional ROM-based phase-to-amplitude conversion circuitry and the linear digital-to-analog converter with a nonlinear digital-to-analog converter (DAC) to realize a simple approximation of the sine function. Thus, the overall power dissipation as well as hardware complexity can be significantly reduced. Besides, by adding the error compensation, the spurious-free dynamic range (SFDR) of the synthesized output signal can be raised drastically.
| Identifer | oai:union.ndltd.org:NSYSU/oai:NSYSU:etd-0711107-185029 |
| Date | 11 July 2007 |
| Creators | Chen, Jian-Ting |
| Contributors | Chua-Chin Wang, Ko-Chi Kuo, Robert Rieger, Jia-Jin chen |
| Publisher | NSYSU |
| Source Sets | NSYSU Electronic Thesis and Dissertation Archive |
| Language | Cholon |
| Detected Language | English |
| Type | text |
| Format | application/pdf |
| Source | http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0711107-185029 |
| Rights | not_available, Copyright information available at source archive |
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