<p>This thesis investigates how systolic architectures can be used in the implementation of an arithmetic unit for small finite fields of characteristic two with polynomial basis representation. </p><p>Systolic architectures provide very high performance but also consume a lot of chip area. A number of design methods for tailoring the systolic arrays for a specified requirement are presented, making it possible to trade throughput, chip area and propagation delays for oneanother. </p><p>A study is also made on how these systolic arrays can be combined to form an arithmetic logic unit, ALU, that canperform operations in many different fields. A number of design alternatives are presented, and an example ALU is presented to give an idea of the performance of such a circuit.</p>
| Identifer | oai:union.ndltd.org:UPSALLA/oai:DiVA.org:liu-1799 |
| Date | January 2003 |
| Creators | Tångring, Ivar |
| Publisher | Linköping University, Department of Electrical Engineering, Institutionen för systemteknik |
| Source Sets | DiVA Archive at Upsalla University |
| Language | English |
| Detected Language | English |
| Type | Student thesis, text |
| Relation | LiTH-ISY-Ex, ; 3396 |
Page generated in 0.0018 seconds