The first topic of this thesis proposes a digital negative phase shifter circuit which generates a clock with adjustable negative delays (phase shift) in order to avoid multi-locking hazards. Arbitrary negative phase can be generated by using multiplexers and voltage variable delay cells to select the required phase shift. The proposed design is implemented by 0.35 um CMOS 1P4M technology. A single-shot locking method is adopted to reduce the locking time. Most important of all, the negative phase shifter is predictable and adjustable. The simulation results show that the accuracy of the proposed design is better than 6%.
The second topic is to describe a 10-bit, 80 MS/s analog-to-digital converter (ADC) for digital video broadcasting over terrestrial (DVB-T) receivers. The ADC is based on a four-channel parallel pipeline architecture which employs dynamic comparators and switch-capacitance sample-and-hold circuit to achieve high speed operation and low power consumption. Simulation results using a TSMC 0.35um 2P4M process show that the proposed ADC achieves 56dB spurious-free dynamic range (SFDR) and 9.01-bit ENOB.
| Identifer | oai:union.ndltd.org:NSYSU/oai:NSYSU:etd-0704105-153105 |
| Date | 04 July 2005 |
| Creators | Hong, Sen-Fu |
| Contributors | Chua-Chin Wang, Shen-Fu Hsiao, Jih-ching Chiu, Sying-Jyan Wang |
| Publisher | NSYSU |
| Source Sets | NSYSU Electronic Thesis and Dissertation Archive |
| Language | Cholon |
| Detected Language | English |
| Type | text |
| Format | application/pdf |
| Source | http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0704105-153105 |
| Rights | not_available, Copyright information available at source archive |
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