Internet of Things (IoT) is a network of devices that are connected through the Internet to exchange the data for intelligent applications. Though IoT devices provide several advantages to improve the quality of life, they also present challenges related to security. The security issues related to IoT devices include leakage of information through Differential Power Analysis (DPA) based side channel attacks, authentication, piracy, etc. DPA is a type of side-channel attack where the attacker monitors the power consumption of the device to guess the secret key stored in it. There are several countermeasures to overcome DPA attacks. However, most of the existing countermeasures consume high power which makes them not suitable to implement in power constraint devices. IoT devices are battery operated, hence it is important to investigate the methods to design energy-efficient and secure IoT devices not susceptible to DPA attacks. In this research, we have explored the usefulness of a novel computing platform called adiabatic logic, low-leakage FinFET devices and Magnetic Tunnel Junction (MTJ) Logic-in-Memory (LiM) architecture to design energy-efficient and DPA secure hardware. Further, we have also explored the usefulness of adiabatic logic in the design of energy-efficient and reliable Physically Unclonable Function (PUF) circuits to overcome the authentication and piracy issues in IoT devices. Adiabatic logic is a low-power circuit design technique to design energy-efficient hardware. Adiabatic logic has reduced dynamic switching energy loss due to the recycling of charge to the power clock. As the first contribution of this dissertation, we have proposed a novel DPA-resistant adiabatic logic family called Energy-Efficient Secure Positive Feedback Adiabatic Logic (EE-SPFAL). EE-SPFAL based circuits are energy-efficient compared to the conventional CMOS based design because of recycling the charge after every clock cycle. Further, EE-SPFAL based circuits consume uniform power irrespective of input data transition which makes them resilience against DPA attacks. Scaling of CMOS transistors have served the industry for more than 50 years in providing integrated circuits that are denser, and cheaper along with its high performance, and low power. However, scaling of the transistors leads to increase in leakage current. Increase in leakage current reduces the energy-efficiency of the computing circuits,and increases their vulnerability to DPA attack. Hence, it is important to investigate the crypto circuits in low leakage devices such as FinFET to make them energy-efficient and DPA resistant. In this dissertation, we have proposed a novel FinFET based Secure Adiabatic Logic (FinSAL) family. FinSAL based designs utilize the low-leakage FinFET device along with adiabatic logic principles to improve energy-efficiency along with its resistance against DPA attack. Recently, Magnetic Tunnel Junction (MTJ)/CMOS based Logic-in-Memory (LiM) circuits have been explored to design low-power non-volatile hardware. Some of the advantages of MTJ device include non-volatility, near-zero leakage power, high integration density and easy compatibility with CMOS devices. However, the differences in power consumption between the switching of MTJ devices increase the vulnerability of Differential Power Analysis (DPA) based side-channel attack. Further, the MTJ/CMOS hybrid logic circuits which require frequent switching of MTJs are not very energy-efficient due to the significant energy required to switch the MTJ devices. In the third contribution of this dissertation, we have investigated a novel approach of building cryptographic hardware in MTJ/CMOS circuits using Look-Up Table (LUT) based method where the data stored in MTJs are constant during the entire encryption/decryption operation. Currently, high supply voltage is required in both writing and sensing operations of hybrid MTJ/CMOS based LiM circuits which consumes a considerable amount of energy. In order to meet the power budget in low-power devices, it is important to investigate the novel design techniques to design ultra-low-power MTJ/CMOS circuits. In the fourth contribution of this dissertation, we have proposed a novel energy-efficient Secure MTJ/CMOS Logic (SMCL) family. The proposed SMCL logic family consumes uniform power irrespective of data transition in MTJ and more energy-efficient compared to the state-of-art MTJ/ CMOS designs by using charge sharing technique. The other important contribution of this dissertation is the design of reliable Physical Unclonable Function (PUF). Physically Unclonable Function (PUF) are circuits which are used to generate secret keys to avoid the piracy and device authentication problems. However, existing PUFs consume high power and they suffer from the problem of generating unreliable bits. This dissertation have addressed this issue in PUFs by designing a novel adiabatic logic based PUF. The time ramp voltages in adiabatic PUF is utilized to improve the reliability of the PUF along with its energy-efficiency. Reliability of the adiabatic logic based PUF proposed in this dissertation is tested through simulation based temperature variations and supply voltage variations.

Weld joint penetration determination is the key factor in welding process control area. Not only has it directly affected the weld joint mechanical properties, like fatigue for example. It also requires much of human intelligence, which either complex modeling or rich of welding experience. Therefore, weld penetration status identification has become the obstacle for intelligent welding system. In this dissertation, an innovative method has been proposed to detect the weld joint penetration status using machine-learning algorithms. A GTAW welding system is firstly built. Project a dot-structured laser pattern onto the weld pool surface during welding process, the reflected laser pattern is captured which contains all the information about the penetration status. An experienced welder is able to determine weld penetration status just based on the reflected laser pattern. However, it is difficult to characterize the images to extract key information that used to determine penetration status. To overcome the challenges in finding right features and accurately processing images to extract key features using conventional machine vision algorithms, we propose using convolutional neural network (CNN) to automatically extract key features and determine penetration status. Data-label pairs are needed to train a CNN. Therefore, an image acquiring system is designed to collect reflected laser pattern and the image of work-piece backside. Data augmentation is performed to enlarge the training data size, which resulting in 270,000 training data, 45,000 validation data and 45,000 test data. A six-layer convolutional neural network (CNN) has been designed and trained using a revised mini-batch gradient descent optimizer. Final test accuracy is 90.7% and using a voting mechanism based on three consequent images further improve the prediction accuracy.

During the operation in a modern power distribution system, some abnormal events may happen, such as over-voltage, faults, under-frequency and overloading, and so on. These abnormal events may cause a power outage in a distribution system or damages on the equipment in a distribution system. Hence these abnormal events should be identified and isolated by protection systems as quickly as possible to make sure we can maintain a stable and reliable distribution system to supply adequate electric power to the largest number of consumers as we can. To sum up, we need stable and reliable protection systems to satisfy this requirement. Chapter 1 of the dissertation is a brief introduction to my research contents. Firstly, the background of a distribution system and the protection systems in a power system will be introduced in the first subchapter. Then there will be a review of existing methods of optimum coordination of overcurrent relays using different optimal techniques. The dissertation outline will be illustrated in the end. Chapter 2 of the dissertation describes a novel method of optimum online adaptive coordination of overcurrent relays using the genetic algorithm. In this chapter, the basic idea of the proposed methods will be explained in the first subchapter. It includes the genetic algorithm concepts and details about how it works as an optimal technique. Then three different types of simulation systems will be used in this part. The first one is a basic distribution system without distributed generations (DGs); the second one is similar to the first one but with load variations; the last simulation system is similar to the first one but with a distributed generation in it. Using three different simulation systems will demonstrate that the coordination of overcurrent relays is influenced by different operating conditions of the distribution system. In Chapter 3, a larger sized distribution system with more distributed generations and loads will be simulated and used for verifying the proposed method in a more realistic environment. In addition, the effects of fault location on the optimum coordination of overcurrent relays will be discussed here. In Chapter 4, the optimal differential evolution (DE) technique will be introduced. Because of the requirement of the online adaptive function, the optimal process needs to be accomplished as soon as possible. Through the comparison between genetic algorithm and differential evolution on the optimum coordination of overcurrent relays, we found that differential evolution is much faster than the genetic algorithm, especially when the size of the distribution system grows. Therefore, the differential evolution optimal technique is more suited than the genetic algorithm to realize online adaptive function. Chapter 5 presents the conclusion of the research work that has been done in this dissertation.

Feeder reconfiguration is performed by changing the open/close status of two types of switches: normally open tie switches and normally closed sectionalizing switches. A whole feeder or part of a feeder may be served from another feeder by closing a tie switch linking the two while an appropriate sectionalizing switch must be opened to maintain the radial structure of the system. Feeder reconfiguration is mainly aiming to reduce the system overall power losses and improve voltage profile. In this dissertation, several approaches have been proposed to reconfigure the radial distribution networks including the potential impact of integrating Distributed Energy Resources (DER) into the grid. These approaches provide a Fast-Genetic Algorithm “FGA” in which the size and convergence speed is improved compared to the conventional genetic algorithm. The size of the population matrix is also smaller because of the simple way of constructing the meshed network. Additionally, FGA deals with integer variable instead of a binary one, which makes FGA a unique method. The number of the mesh/loop is based on the number of tie switches in a particular network. The validity of the proposed FGA is investigated by comparing the obtained results with the one obtained from the most recent approaches. The second the approach is the implementation of the Differential Evolution (DE) algorithm. DE is a population-based method using three operators including crossover, mutation, and selection. It differs from GA in that genetic algorithms rely on crossover while DE relies on mutation. Mutation is based on the differences between randomly sampled pairs of solutions in the population. DE has three advantages: the ability to find the global optimal result regardless of the initial values, fast convergence, and requirement of a few control parameters. DE is a well-known and straightforward population-based probabilistic approach for comprehensive optimization. In distribution systems, if a utility company has the right to control the location and size of distributed generations, then the location and size of DGs may be determined based on some optimization methods. This research provides a promising approach to finding the optimal size and location of the planned DER units using the proposed DE algorithm. DGs location is obtained using the sensitivity of power losses with respect to real power injection at each bus. Then the most sensitive bus is selected for installing the DG unit. Because the integration of the DG adds positive real power injections, the optimal location is the one with the most negative sensitivity in order to get the largest power loss reduction. Finally, after the location is specified, the proposed Differential Evolution Algorithm (DEA) is used to obtain the optimal size of the DG unit. Only the feasible solutions that satisfy all the constraints are considered. The objective of installing DG units to the distribution network is to reduce the system losses and enhance the network voltage profile. Nowadays, these renewable DGs are required to equip with reactive power devices (such as static VAR compensators, capacitor banks, etc.), to provide reactive power as well as to control the voltage at their terminal bus. DGs have various technical benefits such as voltage profile improvement, relief in feeder loading, power loss minimization, stability improvement, and voltage deviation mitigation. The distributed generation may not achieve its full potential of benefits if placed at any random location in the system. It is necessary to investigate and determine the optimum location and size of the DG. Most distribution networks are radial in nature with limited short-circuit capacity. Therefore, there is a limit to which power can be injected into the distribution network without compromising the power quality and the system stability. This research is aiming to investigate this by applying DG technologies to the grid and keeping the system voltage within a defined boundary [0.95 - 1.05 p.u]. The requirements specified in IEEE Standard 1547 are considered. This research considers four objectives related to minimization of the system power loss, minimization of the deviations of the nodes voltage, minimization of branch current constraint violation, and minimization of feeder’s currents imbalance. The research formulates the problem as a multi-objective problem. The effectiveness of the proposed methods is demonstrated on different revised IEEE test systems including 16 and 33-bus radial distribution system.

Accurate value of transmission line parameters is important for power system protection applications, especially for distance relays whose zone settings are based on positive sequence line impedance. The research is devoted to estimating transmission line positive-sequence parameters from synchronized or unsynchronized measurements of voltage and current phasors that are obtained at both terminals of the line. The positive sequence parameters including series impedance and shunt admittance can be linearly estimated. The linear least square algorithm has been derived in this dissertation for different transmission line configurations. The algorithm is able to handle both synchronized and unsynchronized measurements and deal with potential synchronization errors by explicitly modeling the synchronization angle. Sample results are reported to demonstrate the effectiveness of the proposed method. Three types of transmission line models depending on line length (long, medium and short) are studied in this dissertation. Chapter 3 uses unsynchronized data for the long transmission line. The derived method can detect the unsynchronized angle and estimate the positive sequence of long line parameters. The proposed method is examined with negative impacts such as errors on currents and voltages data. These errors are added randomly to one set each time to test the robustness of the developed algorithm. The medium transmission line algorithm derivation is presented in chapter 4. This chapter uses a linear least square to estimate the lumped parameters of a medium transmission line. The two different transmission line circuits are used to model the medium line. The first circuit is a single transmission line with two nodes and is used to evaluate the developed algorithm. The second circuit is a double transmission line. These two lines can have the same or different line parameters or line length. The developed algorithm shows that the proposed method achieves highly accurate results for the estimation of positive sequence line parameters. The short transmission line is studied in chapter 5. The short transmission line uses less data than the long or medium lines because in this model the shunt capacitance is omitted. Thus, the linear estimation yields highly accurate results. Case studies are considered to test the robustness of this developed method. The line temperature mainly affects the series resistance, and the developed algorithms in previous three chapters can accurately estimate the transmission line parameters. To simplify the real-time estimation of line resistance and temperature, the series inductance, and shunt capacitance can be treated as constant and known values. Chapter 6 provides such studies of estimating resistance by treating inductance and capacitance as known values.

Solar energy as the most abundant source of energy is clean, non-pollutant, and completely renewable, which provides energy security, independence, and reliability. Organic-inorganic hybrid perovskite solar cells (PSCs) revolutionized the photovoltaics field not only by showing high efficiency of above 22% in just a few years but also by providing cheap and facile fabrication methods. In this dissertation, fabrication of PSCs in both ambient air conditions and environmentally controlled N2-filled glove-box are studied. Several characterization methods such as SEM, XRD, EDS, Profilometry, four-point probe measurement, EQE, and current-voltage measurements were employed to examine the quality of thin films and the performance of the PSCs. A few issues with the use of equipment for the fabrication of thin films are addressed, and the solutions are provided. It is suggested to fabricate PSCs in ambient air conditions entirely, to reduce the production cost. So, in this part, the preparation of the solutions, the fabrication of thin films, and the storage of materials were performed in ambient air conditions regardless of their humidity sensitivity. Thus, for the first part, the fabrication of PSCs in ambient air conditions with relative humidity above ~36% with and without moisture sensitive material, i.e., Li-TFSI are provided. Perovskite materials including MAPbI3 and mixed cation MAyFA(1-y)PbIxBr(1-x) compositions are investigated. Many solution-process parameters such as the spin-coating speed for deposition of the hole transporting layer (HTL), preparation of the HTL solution, impact of air and light on the HTL conductivity, and the effect of repetitive measurement of PSCs are investigated. The results show that the higher spin speed of PbI2 is critical for high-quality PbI2 film formation. The author also found that exposure of samples to air and light are both crucial for fabrication of solar cells with larger current density and better fill factor. The aging characteristics of the PSCs in air and vacuum environments are also investigated. Each performance parameter of air-stored samples shows a drastic change compared with that of the vacuum-stored samples, and both moisture and oxygen in air are found to influence the PSCs performances. These results are essential towards the fabrication of low-cost, high-efficiency PSCs in ambient air conditions. In the second part, the research is focused on the fabrication of high-efficiency PSCs using the glove-box. Both single-step and two-step spin-coating methods with perovskite precursors such as MAyFA(1-y)PbIxBr(1-x) and Cesium-doped mixed cation perovskite with a final formula of Cs0.07MA0.1581FA0.7719Pb1I2.49Br0.51 were considered. The effect of several materials and process parameters on the performance of PSCs are investigated. A new solution which consists of titanium dioxide (TiO2), hydrochloric acid (HCl), and anhydrous ethanol is introduced and optimized for fabrication of quick, pinhole-free, and efficient hole-blocking layer using the spin-coating method. Highly reproducible PSCs with an average power conversion efficiency (PCE) of 15.4% are fabricated using this solution by spin-coating method compared to the conventional solution utilizing both spin-coating with an average PCE of 10.6% and spray pyrolysis with an average PCE of 13.78%. Moreover, a thin layer of silver is introduced as an interlayer between the HTL and the back contact. Interestingly, it improved the current density and, finally the PCEs of devices by improving the adhesion of the back electrode onto the organic HTL and increasing the light reflection in the PSC. Finally, a highly reproducible fabrication procedure for cesium-doped PSCs using the anti-solvent method with an average PCE of 16.5%, and a maximum PCE of ~17.5% is provided.

Spatial augmented reality is a particular kind of augmented reality technique that uses projector to blend the real objects with virtual contents. Coincidentally, as a means of 3D shape measurement, structured light illumination makes use of projector as part of its system as well. It uses the projector to generate important clues to establish the correspondence between the 2D image coordinate system and the 3D world coordinate system. So it is appealing to build a system that can carry out the functionalities of both spatial augmented reality and structured light illumination. In this dissertation, we present all the hardware platforms we developed and their related applications in spatial augmented reality and structured light illumination. Firstly, it is a dual-projector structured light 3D scanning system that has two synchronized projectors operate simultaneously, consequently it outperforms the traditional structured light 3D scanning system which only include one projector in terms of the quality of 3D reconstructions. Secondly, we introduce a modified dual-projector structured light 3D scanning system aiming at detecting and solving the multi-path interference. Thirdly, we propose an augmented reality face paint system which detects human face in a scene and paints the face with any favorite colors by projection. Additionally, the system incorporates a second camera to realize the 3D space position tracking by exploiting the principle of structured light illumination. At last, a structured light 3D scanning system with its own built-in machine vision camera is presented as the future work. So far the standalone camera has been completed from the a bare CMOS sensor. With this customized camera, we can achieve high dynamic range imaging and better synchronization between the camera and projector. But the full-blown system that includes HDMI transmitter, structured light pattern generator and synchronization logic has yet to be done due to the lack of a well designed high speed PCB.

Most systems in HPC make use of hierarchical designs that allow multiple levels of parallelism to be exploited by programmers. The use of multiple multi-core/multi-processor computers to form a computer cluster supports both fine-grain and large-grain parallel computation. Aggregate function communications provide an easy to use and efficient set of mechanisms for communicating and coordinating between processing elements, but the model originally targeted only fine grain parallel hardware. This work shows that a hierarchical implementation of aggregate functions is a viable alternative to MPI (the standard Message Passing Interface library) for programming clusters that provide both fine grain and large grain execution. Performance of a prototype implementation is evaluated and compared to that of MPI.

CMOS based computing is reaching its limits. To take computation beyond Moores law (the number of transistors and hence processing power on a chip doubles every 18 months to 3 years) requires research explorations in (i) new materials, devices, and processes, (ii) new architectures and algorithms, (iii) new paradigm of logic bit representation. The focus is on fundamental new ways to compute under the umbrella of rebooting computing such as spintronics, quantum computing, adiabatic and reversible computing. Therefore, this thesis highlights explicitly Quantum computing and Adiabatic logic, two new computing paradigms that come under the umbrella of rebooting computing. Quantum computing is investigated for its promising application in high-performance computing. The first contribution of this thesis is the design of two resource-efficient designs for quantum integer division. The first design is based on non-restoring division algorithm and the second one is based on restoring division algorithm. Both the designs are compared and shown to be superior to the existing work in terms of T-count and T-depth. The proliferation of IoT devices which work on low-power also has drawn interests to the rebooting computing. Hence, the second contribution of this thesis is proving that Adiabatic Logic is a promising candidate for implementation in IoT devices. The adiabatic logic family called Symmetric Pass Gate Adiabatic Logic (SPGAL) is implemented in PRESENT-80 lightweight algorithm. Adiabatic Logic is extended to emerging transistor devices.

Power system faults normally result in system damage, profit loss and consumer dissatisfaction. Consequently, there is a strong demand on precise and fast fault location estimation for power system to minimize the system restoration time. This paper examines a method to locate short-circuit faults on a distribution system with unbalanced loads without fault type information. Bus impedance matrix technique was harnessed in the fault location estimation algorithm. The system data including line impedances, source impedance and distribution system layout was assumed to be known factors, hence pre-fault bus impedance can be calculated and implemented into the algorithm. Corresponding methods to derive system matrix information were discussed. Case studies were performed to evaluate the accuracy of the fault location algorithm and illustrate the robust performance under measurements errors influences, load variation impacts and load compensation implementations. Traditional fault location methods involve current and voltage measurements mandatorily locating at each ends of faulted section to locate the fault. The method examined finds fault location for distribution system utilizing impedance matrix accompanied with sparse measurements in the power network. This method fully considers the unbalance of distribution system.