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Dynamically reconfigurable intellectual property coresMacBeth, John Stuart January 2003 (has links)
No description available.
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Design and implementation of a high level image processing machine using reconfigurable hardwareDonachy, Paul January 1996 (has links)
No description available.
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Scan path design of PLA to improve its testability in VLSI realizationChiang, Kang-Chung. January 1986 (has links)
Thesis (M.S.)--Ohio University, August, 1986. / Title from PDF t.p.
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Using FPGA Co-processors for Improving the execution Speed of Pattern Recognition Algorithms in ATLAS LVL2 TriggerKhomich, Andrei. January 2006 (has links)
Mannheim, Univ., Diss., 2006.
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Building concept images : supercalculators and students' use of multiple representations in calculus /Hart, Dianne K. January 1991 (has links)
Thesis (Ph. D.)--Oregon State University, 1992. / Typescript (photocopy). Includes bibliographical references (leaves 292-297). Also available on the World Wide Web.
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Using instructional design to resolve a problem in teaching programmable automation to baccalaureate industrial technology studentsStier, Kenneth W. Rhodes, Dent. January 1989 (has links)
Thesis (Ed. D.)--Illinois State University, 1989. / Title from title page screen, viewed November 1, 2005. Dissertation Committee: Dent M. Rhodes (chair), Franzie L. Loepp, Walter D. Pierce, Henry L. Thomas. Includes bibliographical references (leaves 248-260) and abstract. Also available in print.
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Managing a reconfigurable processor in a general purpose workstation environmentDales, Michael Winston. January 2003 (has links)
Thesis (Ph. D.)--University of Glasgow, 2003. / Includes bibliographical references. Print version also available.
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Exploring Memristor Based Analog Design in SimscapeGautam, Mahesh 05 1900 (has links)
With conventional CMOS technologies approaching their scaling limits, researchers are actively investigating alternative technologies for ever increasing computing and mobile demand. A number of different technologies are currently being studied by different research groups. In the last decade, one-dimensional (1D) carbon nanotubes (CNT), graphene, which is a two-dimensional (2D) natural occurring carbon rolled in tubular form, and zero-dimensional (0D) fullerenes have been the subject of intensive research. In 2008, HP Labs announced a ground-breaking fabrication of memristors, the fourth fundamental element postulated by Chua at the University of California, Berkeley in 1971. In the last few years, the memristor has gained a lot of attention from the research community. In-depth studies of the memristor and its analog behavior have convinced the community that it has the potential in future nano-architectures for optimization of high-density memory and neuromorphic computing architectures. The objective of this thesis is to explore memristors for analog and mixed-signal system design using Simscape. This thesis presents a memristor model in the Simscape language. Simscape has been used as it has the potential for modeling large systems. A memristor based programmable oscillator is also presented with simulation results and characterization. In addition, simulation results of different memristor models are presented which are crucial for the detailed understanding of the memristor along with its properties.
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DESIGN OF A PROGRAMMABLE ROUTING FRAMEWORK FOR MULTI-TECHNOLOGY FIELD PROGRAMMABLE GATE ARRAYHAWK, CHRISTOPHER J. 31 March 2004 (has links)
No description available.
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Analog signal processing on a reconfigurable platformSchlottmann, Craig Richard 08 July 2009 (has links)
The Cooperative Analog/Digital Signal Processing (CADSP) research group's approach to signal processing is to see what opportunities lie in adjusting the line between what is traditionally computed in digital and what can be done in analog. By allowing more computation to be done in analog, we can take advantage of its low power, continuous domain operation, and parallel capabilities. One setback keeping Analog Signal Processing (ASP) from achieving more wide-spread use, however, is its lack of programmability. The design cycle for a typical analog system often involves several iterations of the fabrication step, which is labor intensive, time consuming, and expensive. These costs in both time and money reduce the likelihood that engineers will consider an analog solution. With CADSP's development of a reconfigurable analog platform, a Field-Programmable Analog Array (FPAA), it has become much more practical for systems to incorporate processing in the analog domain. In this Thesis, I present an entire chain of tools that allow one to design simply at the system block level and then compile that design onto analog hardware. This tool chain uses the Simulink design environment and a custom library of blocks to create analog systems. I also present several of these ASP blocks, covering a broad range of functions from matrix computation to interfacing. In addition to these tools and blocks, the most recent FPAA architectures are discussed. These include the latest RASP general-purpose FPAAs as well as an adapted version geared toward high-speed applications.
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