Field programmable gate arrays are a class of integrated circuit that enable logic functions and interconnects to be programmed in almost real time. They can implement fine grained parallel computing architectures and algorithms in hardware that were previously the domain of custom VLSI. Field programmable gate arrays have shown themselves useful at exploiting concurrency in a range of applications such as text searching, image processing and encryption. When coupled with a microprocessor, which is more suited to computation involving complex control flow and non time critical requirements, they form a potentially versatile platform commonly known as a Reconfigurable Computer. Reconfigurable computing applications have traditionally had the exclusive use of the field programmable gate array, primarily because the logic densities of the available devices have been relatively similar in size compared to the application. But with the modern FPGA expanding beyond 10 million system gates, and through the use of dynamic reconfiguration, it has become feasible for several applications to share a single high density device. However, developing applications that share a device is difficult as the current design flow assumes the exclusive use of the FPGA resources. As a consequence, the designer must ensure that resources have been allocated for all possible combinations of loaded applications at design time. If the sequence of application loading and unloading is not known in advance, all resource allocation cannot be performed at design time because the availability of resources changes dynamically. The use of a runtime resource allocation environment modelled on a classical software operating system would allow the full benefits of dynamic reconfiguration on high density FPGAs to be realised. In addition to runtime resource allocation, other services provided by an operating system such as abstraction of I/O and inter-application communication would provide additional benefits to the users of a reconfigurable computer. This could possibly reduce the difficulty of application development and deployment. In this thesis, an operating system for reconfigurable computing that supports dynamically arriving applications is presented. This is achieved by firstly developing the abstractions with which designers implement their applications and a set of algorithm requirements that specify the resource allocation and logic partitioning services. By combining these, an architecture of an operating system for reconfigurable computing can be specified. A prototype implementation on one platform with multiple applications is then presented which enables an exploration of how the resource allocation algorithms interact amongst themselves and with typical applications. Results obtained from the prototype include the measurement of the performance loss in applications, and the time overheads introduced due to the use of the operating system. Comparisons are made with programmable logic applications run with and without the operating system. The results show that the overheads are reasonable given the current state of the technology of FPGAs. Formulas for predicting the user response time and application throughput based on the fragmentation of an FPGA are then derived. Weaknesses are highlighted in the current design flows and the architecture of current FPGAs must be rectified if an operating system is to become main-stream. For the tool flows this includes the ability to pre-place and pre-route cores and perform high speed runtime routing. For the FPGAs these include an optimised network, a memory management core, and a separate layer to handle dynamic routing of the network. / thesis (PhD)--University of South Australia, 2005.

Thesis (Ph. D.)--University of Texas at Dallas, 2006. / Includes vita. Includes bibliographical references (leaves 173-178).

Denna rapport presenterar en metod som möjliggör bestämning av bredbandiga signalers infallsvinklar. Studien är gjord i Matlab där infallande signaler samplades med ett antal sensorer utplacerade ekvidistant på en rätlinje. Den samplade informationen viktades sedan med konstanter framtagna med en konvex optimeringsrutin för att bilda en vinkelberoende utsignal. Rutinerna testades för insignaler med ett få antal frekvenser och gav för alla testade insgnaler en mycket bra bestämmning av infallsvinklen. Studien visar även att det är möjligt att göra systemet mer robust mot störningar i sensorernas positioner genom att ställa kriterier på den konvexa optimerings rutinen.

Digital Clay is a tactile array of linear fluidic actuators which provide distributed sensing and position control through the use of an embedded position sensor. The actuator implementation is achieved by two-way hydraulically-driven pistons which are integrated with computer controlled valves. Each actuator is connected to an underlying base plate which is in fluidic communication with high and low pressure reservoirs. The research focuses on the aspects of the fluidics necessary to operate the actuators and control actuation of Digital Clay. The main objectives of this work are the characterization of the fluid flow through the system and the design and implementation of an embedded inductance-based position sensor. Each actuator in Digital Clay is individually addressable and is controlled through the use of a closed-loop proportional integral controller with position feedback from the embedded inductance-based sensor. Also presented in this work is the characterization of an individual fluidic actuator and the realization of a 5x5 tactile array of actuators.

Here choose wedge-shaped fiber, which have sample shape, low manufacture cost and time, to manufacture wedge-shaped fiber array in the paper. In order to reduce cost, it depends on change and reduce manufacture process steps.

Thesis (Ph. D.)--University of Texas at Austin, 1999. / Vita. Includes bibliographical references (leaves 212-225). Available also in a digital version from Dissertation Abstracts.

Thesis (M.S. in Engineering Science)--Naval Postgraduate School, December 2003. / Thesis advisor(s): David C. Jenn, Roberto Cristi. Includes bibliographical references (p. 95). Also available online.

Not available / text

Acoustic Receiving Line Arrays are critical tools for measuring the acoustic properties of any oceanographic region. Vertical, horizontal, and combinations of the two array configurations allow us to measure acoustic propagation, bottom characteristics through inversion, and ambient noise. These properties are vitally important for effective implementation of any passive or active detection system in both shallow and deep water environments. Measurement systems must be designed with flexibility since the exact array design that yields the best signal processing results is not known prior to a survey. Flexibility, in this case, refers to large numbers of hydrophones, higher sample rates for greater bandwidth, and longer recording time to facilitate experimentation at each survey site. Repeated deployment and recovery of such a system demands a battery powered autonomous design that can be deployed and recovered from available research vessels at sea. Conventional deep ocean analog array cable designs, while power efficient, become physically challenging in size and weight when the sensor count exceeds 100 and array lengths remain in the 100s of meters. The purpose of this thesis is to detail the design, development, and testing of a pressure tolerant full ocean depth rated prototype acoustic line array with digital telemetry of all hydrophone data from the sensors to the recording system. The design is to support up to 300 hydrophones each with a maximum sample rate of 4 kHz and a per sensor power requirement of ¾ of a watt. Lower sensor counts will allow higher sample rates to be used based on available telemetry bandwidth. A single element of a line array was built and tested at the University of Texas at Austin Applied Research Laboratories and it was used to demonstrate real-time telemetry and recording of acoustic hydrophone data. / text

The contribution of the work here presented involves three main topics: Wireless Power Transmission (WPT) technology, phased array systems, and microwave components design and modeling. The first topic presents the conceptual design of a WPT system at 2.45GHz with 90% efficiency and 1MW of DC output power. Second, a comparative study between 2.45 and 35GHz WPT operation is provided. Finally, the optimization of a taper distribution with reduced thermal constraints on a sandwich transmitter is realized. For a 250- and 375-m antenna radius, 89.7% of collection efficiency with 29% reduction in maximum power density (compared to the Gaussian), and 93% collection efficiency with 39% reduction of maximum power density, are obtained respectively with two split tapers. The reduction in maximum power density and the use of split taper are important to alleviate the thermal problems in high power transmission. For the phased array project, the conceptual design of a small-scale system and in-depth analysis using two main approaches (statistical and field analysis) is realized. Practical aspects are addressed to determine the phased array main design features. The statistical method provides less accurate results than the field analysis since it is intended for large arrays. Careful theoretical analysis led to good correlation between statistical, field analysis and experimental results. In the components chapter, efficient loop transitions used in a patch antenna array are designed at K- and W-band. Measured insertion loss (IL) K-band loop is under 0.4dB. The K- and W-band antenna array measured broadside gains are 23.6dB at 24.125GHz and 25dB at 76.5GHz with return loss under 9.54dB from 24 to 24.4GHz and 12 dB from 75.1 to 77.3GHz, respectively. Also, a multilayer folded line filter is designed at 5.8GHz and compared to planar ring filters. Improved measured bandwidth from 2GHz to 7.5GHz and IL of 1.2dB are obtained with approximately half the size of a planar ring resonator. Thirdly, a simplified switch model is implemented for use in broadband phased-shifters. The model presents very good fit to the measured results with an overall total error under 3%, magnitude error less than 8%, and phase errors less than ±0.4°.