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As the use of digital systems continues to grow, there is an increasing need to convert analog information into the digital domain. Successive Approximation Register (SAR) analog-to-digital converters are used extensively in this regard due to their high resolution, small die area, and moderate conversion speeds. However, capacitor mismatch within the SAR converter is a limiting factor in its accuracy and resolution. Without some form of calibration, a SAR converter can only reasonably achieve an accuracy of 10 bits. The Split-ADC technique is a digital, deterministic, background self-calibration algorithm that can be applied to the SAR converter. This thesis describes the circuit design and physical implementation of a novel 16-bit 1MS/s SAR analog-to-digital converter for use with the Split-ADC calibration algorithm. The system was designed using the Jazz 0.18um CMOS process, successfully operates at 1MS/s, and consumes a die area of 1.2mm2. The calibration algorithm was applied, showing an improvement in the overall accuracy of the converter.

Aujourd’hui, l’amélioration des fréquences de coupure des transistors MOS et bipolaires ouvre la voie à de nouvelles applications THz (communication et imagerie au-delà de 110 GHz). Des méthodologies de test concernant la caractérisation en bruit hyperfréquence des transistors jusque 170 GHz ont été mises en place dans la cadre du laboratoire commun entre STMicroelectronics et l’IEMN. Cependant, une des limitations principales à la conception d’un outil de caractérisation en bruit au-delà de 170 GHz est le manque de source de bruit état-solide à ces fréquences. Cette thèse propose un nouveau type de source de bruit aux fréquences millimétriques pouvant fonctionner au-delà de 170 GHz, basée sur une solution photonique intégrée sur silicium. Cette source de bruit photonique repose sur l’éclairage d’une photodiode en germanium sur silicium par une source optique qui sera alors convertit en un bruit blanc électrique. / Today high frequency MOS and bipolar transistors are opening new opportunities for THZ applications (communication and imagery beyond 110 GHz). High frequency noise characterization test methodologies up to 170 GHz have been set up in a shared collaboration between STMicroelectronics and IEMN laboratory. Nevertheless, one of the most important limitations of noise characterization above 170 GHz is the solid-state noise source lack at these frequencies. This study proposes a new concept of noise source working at millimeter wave frequencies above 170 GHz, based on a photonic integrated on silicon solution. This photonics noise source concept relies on a Germanium-on-Silicon photodiode lighted by an optical source and converting it into an electrical noise.

The aim of the thesis is to develop a model-based control strategy, namely, the Model Predictive Control (MPC) method, for robot position control using artificial neural networks. MPC is primarily developed for process control. Therefore its application in robot control has been less reported. In addition, conventional MPC uses linear model of the system for prediction which leads to inaccuracy for highly non-linear systems, such as robot. In this thesis a simulation model of a modified PUMA robot is constructed. This model is built using both MATLAB/SIMULINK and FORTRAN languages. In this model, the full robot dynamics is used together with the realistic factors, such as the actuator effects and the gear backlash, to represent the real system accurately. All simulations throughout this thesis are carried out on this model. A model predictive control strategy for robot trajectory tracking is also introduced in this thesis. The feasibility of the proposed MPC control method is studied based on a perfect prediction model, a model with uncertainties, and when the frequency band of the MPC controller is limited. Furthermore, a new method of using neural networks for robot dynamics modelling is introduced. This method is developed on the basis of a numerical differential technique that eliminates the explicit requirement of robot joint accelerations. Therefore, this method can be easily implemented on physical systems. As the measurements of the robot joint positions, velocities, and torques collected from operating the robot can be used to train the neural network, a more accurate dynamic model can be obtained. Finally, the MPC control method and the neural network model are combined together to form a neural network based MPC controller. The validity of this method is verified by using simulation on the simulated robot system / Master of Engineering (Hons)

Thesis (Ph. D.)--University of Texas at Austin, 2006. / Vita. Includes bibliographical references.

Ph.D. / Electrical Engineering / The expected unreliability of nano-scale electronic components has renewed interest in the decades-old field of fault-tolerant logic design. Fault-tolerant design makes it possible to build reliable systems from unreliable components. This has spurred recent research into the application of classical FT techniques to nanoelectronics. Meanwhile, the growing gap between logic gate and wire delays, and the growing power consumption of clock generation and distribution circuits, in nanometer-scale silicon integrated circuits has renewed research in asynchronous, or clockless, logic design. This dissertation examines the application of triple modular redundancy (TMR), one of several FT circuit design techniques, to improve the reliability of a variety of clockless circuits and systems. A new fault model, appropriate for clockless circuits is derived and applied to measure the reliability of nonredundant and triplex micropipelines. A new circuit element that combines the functionality of a Muller C-element and a majority gate is introduced to solve special problems at the simplex-triplex interface. The effectiveness of asynchronous FT circuit design strategies based on the results of Monte Carlo simulation experiments with representative circuits modeled in Verilog hardware description language (HDL) is presented.