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Thesis (M.F.A.)--Boston University / PLEASE NOTE: Boston University Libraries did not receive an Authorization To Manage form for this thesis or dissertation. It is therefore not openly accessible, though it may be available by request. If you are the author or principal advisor of this work and would like to request open access for it, please contact us at open-help@bu.edu. Thank you. / 2031-01-01

Thesis (Ph.D.)--University of Delaware, 2007. / Principal faculty advisor: Fouad Kiamilev, Dept. of Electrical and Computer Engineering. Includes bibliographical references.

The electrical behavior of on-chip interconnects has become a dominant factor in silicon-based high speed, RF, and mixed-signal integrated circuits. In particular, the frequency-dependent loss mechanisms in heavily-doped silicon substrates can have a large influence on the transmission characteristics of on-chip interconnects. To optimize the performance of the integrated circuit, efficient interconnect models should be available in the design environment. Interconnect models in the form of closed-form expressions or ideal element equivalent circuits are often desirable for fast simulation and circuit optimization. This thesis work is concentrated on the analysis and the methodology for developing closed-form expressions for the frequency-dependent line parameters R(��), L(��), G(��), and C(��) for coplanar-type on-chip interconnects on silicon substrates. In addition, the closed-form expressions for the frequency-dependent series impedance parameters are extended to general interconnect on-chip structures on multilayer substrates. The complete solutions of the frequency-dependent line parameters are formulated in terms of corresponding static (lossless) configurations for which closed-form solutions are readily available. The closed-form expressions for the frequency-dependent series impedance parameters, R(��) and L(��), are obtained from a generalized complex image approach together with a surface impedance formulation including the effects of the frequency-dependent horizontal currents (eddy currents) in the multilayer lossy silicon substrates. Results for single and coupled microstrips on multilayer silicon substrates are shown over a broadband frequency range of 20 GHz and compared with full-wave electromagnetic solutions. For single and coupled coplanar on-chip interconnects, the results are compared with quasi-analytical solutions and validated with available measurement data. The frequency-dependent shunt admittance parameters, G(��) and C(��), are derived in terms of low- and high-frequency asymptotic solutions of the equivalent circuit model combined with the complex image method. Comparisons and validation with measurements are also presented. / Graduation date: 2004

The electrical performance of on-chip interconnects has become a limiting factor to the performance of modern integrated circuits including RFICs, mixed-signal circuits, as well as high-speed VLSI circuits due to increasing operating frequencies, chip areas, and integration densities. It is advantageous to have fast and accurate closed-form expressions for the characteristics of on-chip interconnects to facilitate fast simulation and computer-aided design (CAD) of integrated circuits. This thesis work is mainly concerned with the analysis and the methodology of developing closed-form expressions for the frequency-dependent line parameters R(��), L(��), G(��), and C(��) for microstrip-type on-chip interconnects on silicon substrate. The complete solutions of the frequency-dependent line parameters are formulated in terms of corresponding lossless/static configurations for both single and coupled microstrip-type on-chip interconnects. The series impedance parameters are developed using a complex image approach, which represents the complicated loss effects in the semiconducting silicon substrate. The shunt admittance parameters are developed using low- and high-frequency asymptotic solutions based on the shunt equivalent circuit models. The closed-form expressions are shown to be in good agreement with full-wave and quasi-static electromagnetic solutions. Based on the proposed closed-form solutions, a new on-chip interconnect extractor tool, CELERITY, is implemented. It is shown that the new tool can significantly reduce the simulation time compared with a quasi-static EM-based tool. The proposed extraction technique should be very useful in the design of silicon-based integrated circuits. / Graduation date: 2002

As a most critical form of pre-silicon verification, transistor-level circuit simulation is an indispensable step before committing to an expensive manufacturing process. However, considering the nature of circuit simulation, it can be computationally expensive, especially for ever-larger transistor circuits with more complex device models. Therefore, it is becoming increasingly desirable to accelerate circuit simulation. On the other hand, the emergence of multi-core machines offers a promising solution to circuit simulation besides the known application of distributed-memory clustered computing platforms, which provides abundant hardware computing resources. This research addresses the limitations of traditional serial circuit simulations and proposes new techniques for both time-domain and frequency-domain parallel circuit simulations. For time-domain simulation, this dissertation presents a parallel transient simulation methodology. This new approach, called WavePipe, exploits coarse-grained application-level parallelism by simultaneously computing circuit solutions at multiple adjacent time points in a way resembling hardware pipelining. There are two embodiments in WavePipe: backward and forward pipelining schemes. While the former creates independent computing tasks that contribute to a larger future time step, the latter performs predictive computing along the forward direction. Unlike existing relaxation methods, WavePipe facilitates parallel circuit simulation without jeopardizing convergence and accuracy. As a coarse-grained parallel approach, it requires low parallel programming effort, furthermore it creates new avenues to have a full utilization of increasingly parallel hardware by going beyond conventional finer grained parallel device model evaluation and matrix solutions. This dissertation also exploits the recently developed explicit telescopic projective integration method for efficient parallel transient circuit simulation by addressing the stability limitation of explicit numerical integration. The new method allows the effective time step controlled by accuracy requirement instead of stability limitation. Therefore, it not only leads to noticeable efficiency improvement, but also lends itself to straightforward parallelization due to its explicit nature. For frequency-domain simulation, this dissertation presents a parallel harmonic balance approach, applicable to the steady-state and envelope-following analyses of both driven and autonomous circuits. The new approach is centered on a naturally-parallelizable preconditioning technique that speeds up the core computation in harmonic balance based analysis. The proposed method facilitates parallel computing via the use of domain knowledge and simplifies parallel programming compared with fine-grained strategies. As a result, favorable runtime speedups are achieved.

This thesis presents an automatic tuning circuit that it is focused on compensation for the filter¡¦s frequency error resulting from the variation of fabrication process, supply voltage and temperature. We utilize a tunable operational transconductance amplifier and a capacitor to form a single-time constant circuit (STC). When we input a reference signal to this circuit, the output of STC circuit can produce a controllable delay time clock. The tuning circuit uses the constant delay time to tune the frequency of the filter. The design of the STC circuit is simple and it has less chip area. All circuits are designed by using the parameters of TSMC 0.35um mixed signal process, and the supply voltage is 3V. The simulation result shows that the filter¡¦s 3-dB frequency error can be controlled by less than 7% as the filter is under the condition of over a range of supply voltages(¡Ó10¢H), operating temperatures(-20 ¢Jto 70¢J ) and five models of SPICE model.

Thesis (Ph. D.)--School of Electrical and Computer Engineering, Georgia Institute of Technology, 2004. Directed by James D. Meindl. / Vita. Includes bibliographical references (leaves 163-169).