Ultra-wideband technology (UWB) has received tremendous attention since the FCC license release in 2002, which expedited the research and development of UWB technologies on consumer products. The applications of UWB range from ground penetrating radar, distance sensor, through wall radar to high speed, short distance communications. The CMOS integrated circuit is an attractive, low cost approach for implementing UWB technology. The improving cut-off frequency of the transistor in CMOS process makes the CMOS circuit capable of handling signal at multi-giga herz. However, some design challenges still remain to be solved. Unlike regular narrow band signal, the UWB signal is discrete pulse instead of continuous wave (CW), which results in the occupancy of wide frequency range. This demands that UWB front-end circuits deliver both time domain and frequency domain signal processing over broad bandwidth. Witnessing these technique challenges, this dissertation aims at designing novel, high performance components for UWB signal generation, down-conversion, as well as accurate timing control using low cost CMOS technology. We proposed, designed and fabricated a carrier based UWB transmitter to facilitate the discrete feature of the UWB signal. The transmitter employs novel twostage -switching to generate carrier based UWB signal. The structure not only minimizes the current consumption but also eliminates the use of a UWB power amplifier. The fabricated transmitter is capable of delivering tunable UWB signal over the complete 3.1GHz -10.6GHz UWB band. By applying the similar two-stage switching approach, we were able to implement a novel switched-LNA based UWB sampling receiver frontend. The proposed front-end has significantly lower power consumption compared to previously published design while keep relatively high gain and low noise at the same time. The designed sampling mixer shows unprecedented performance of 9-12dB voltage conversion gain, 16-25dB noise figure, and power consumption of only 21.6mW(with buffer) and 11.7mW(without buffer) across dc to 3.5GHz with 100M-Hz sampling frequency. The implementation of a precise delay generator is also presented in the dissertation. It relies on an external reference clock to provide accurate timing against process, supply voltage and temperature variation through a negative feedback loop. The delay generator prototype has been verified having digital programmability and tunable delay step resolution. The relative delay shift from desired value is limited to within 0.2%.

Circuit breakers are used in a power system to break or make current flow through power system apparatus. Reliable operation of circuit breakers is very important to the well-being of the power system. Historically this is achieved by regular inspection and maintenance of the circuit breakers. An automated online circuit breaker monitoring system is proposed to monitor condition, operation and status of high and medium voltage circuit breakers. By tracking equipment condition, this system could be used to perform maintenance only when it is needed. This could decrease overall maintenance cost and increase equipment reliability. Using high accurate time synchronization, this system should enable development of system-wide applications that utilize the data recorded by the system. This makes possible tracking sequence of events and making conclusions about their effect on-line. This solution also enables reliable topology analysis, which can be used to improve power flow analysis, state estimation and alarm processing.

New maintenance techniques for circuit breakers are studied in this dissertation by proposing a probabilistic maintenance model and a new methodology to assess circuit breaker condition utilizing its control circuit data. A risk-based decision approach is proposed at system level making use of the proposed new methodology, for optimizing the maintenance schedules and allocation of resources. This dissertation is focused on developing optimal maintenance strategies for circuit breakers, both at component and system level. A probabilistic maintenance model is proposed using similar approach recently introduced for power transformers. Probabilistic models give better insight into the interplay among monitoring techniques, failure modes and maintenance techniques of the component. The model is based on the concept of representing the component life time by several deterioration stages. Inspection and maintenance is introduced at each stage and model parameters are defined. A sensitivity analysis is carried to understand the importance of model parameters in obtaining optimal maintenance strategies. The analysis covers the effect of inspection rate calculated for each stage and its impact on failure probability, inspection cost, maintenance cost and failure cost. This maintenance model is best suited for long-term maintenance planning. All simulations are carried in MATLAB and how the analysis results may be used to achieve optimal maintenance schedules is discussed. A new methodology is proposed to convert data from the control circuit of a breaker into condition of the breaker by defining several performance indices for breaker assemblies. Control circuit signal timings are extracted and a probability distribution is fitted to each timing parameter. Performance indices for various assemblies such as, trip coil, close coil, auxiliary contacts etc. are defined based on the probability distributions. These indices are updated using Bayesian approach as the new data arrives. This process can be made practical by approximating the Bayesian approach calculating the indices on-line. The quantification of maintenance is achieved by computing the indices after a maintenance action and comparing with those of previously estimated ones. A risk-based decision approach to maintenance planning is proposed based on the new methodology developed for maintenance quantification. A list of events is identified for the test system under consideration, and event probability, event consequence, and hence the risk associated with each event is computed. Optimal maintenance decisions are taken based on the computed risk levels for each event. Two case studies are presented to evaluate the performance of the proposed new methodology for maintenance quantification. The risk-based decision approach is tested on IEEE Reliability Test System. All simulations are carried in MATLAB and the discussions of results are provided.

The efficiency of compiling high-level quantum algorithms into instruction sets native to quantum computers defines the moment in the future when we will be able to solve interesting and important problems on quantum computers. In my work I focus on the new methods for compiling single qubit operations that appear in many quantum algorithms into single qubit operations natively supported by several popular architectures. In addition, I study several questions related to synthesis and optimization of multiqubit operations. When studying the single qubit case, I consider two native instruction sets. The first one is Clifford+T; it is supported by conventional quantum computers implementing fault tolerance protocols based on concatenated and surface codes, and by topological quantum computers based on Ising anyons. The second instruction set is the one supported by topological quantum computers based on Fibonacci anyons. I show that in both cases one can use the number theoretic structure of the problem and methods of computational algebraic number theory to achieve improvements over the previous state of the art by factors ranging from 10 to 1000 for instances of the problem interesting in practice. This order of improvement might make certain interesting quantum computations possible several years earlier. The work related to multiqubit operations is on exact synthesis and optimization of Clifford+T and Clifford circuits. I show an exact synthesis algorithm for unitaries generated by Clifford+T circuits requiring exponentially less number of gates than previous state of the art. For Clifford circuits two directions are studied: the algorithm for finding optimal circuits acting on a small number of qubits and heuristics for larger circuits optimization. The techniques developed allows one to reduce the size of encoding and decoding circuits for quantum error correcting codes by 40-50\% and also finds their applications in randomized benchmarking protocols.

The use of generator circuit breakers in power stations was investigated and evaluated. A feasibility study to determine if the additional capital cost required, when using a generator circuit breaker in a power station could be justified by the advantages it provides. The background to the study is provided through a technology and literature survey. Included in the technology review and the literature study is information on interruption mediums, the historic developments of circuit breakers and generator circuit breaker application theory. This data was used to determine the practicality of using a specific interruption medium within a generator circuit breaker application. The requirements of generator circuit breakers were determined and used to evaluate the interruption mediums in question. To ensure practical results, commonly used layouts were used to determine the effect of using a generator circuit breaker on the reliability, availability and the mean time to repair of a power station electrical distribution layout. Furthermore, the effect of the protection on the generator and generator transformer was evaluated. It was found that increased selectivity of the protection system by using a generator circuit breaker limits the extent of equipment damage in case of failure. Practical layouts were used to determine the effect on reliability. The analysis was conducted using assumed values of operational costs to determine the cost incurred through the change in reliability of the power station. By adding a generator circuit breaker, the station transformer and associated equipment is regarded as back-up or redundant equipment. This increases the reliability of the power station dramatically and limits the risk of income lost due to failures. The full evaluation included the estimation of the capital investment costs and the impact that the additional cost has on the operational requirements of a power station. The study determined that the capital cost required to use a generator circuit breaker results in no additional income for a power station. Through the increased protection, higher availability and the possible omission of power station ancillary equipment, the use of generator circuit breakers will result in more power being delivered and more income generated by a power station. The study proved that the generator circuit breaker is a critical part of a power station layout and is a necessary capital requirement to ensure the sustainability of the power station. / Thesis (M.Ing. (Electrical and Electronic Engineering))--North-West University, Potchefstroom Campus, 2010.

The use of generator circuit breakers in power stations was investigated and evaluated. A feasibility study to determine if the additional capital cost required, when using a generator circuit breaker in a power station could be justified by the advantages it provides. The background to the study is provided through a technology and literature survey. Included in the technology review and the literature study is information on interruption mediums, the historic developments of circuit breakers and generator circuit breaker application theory. This data was used to determine the practicality of using a specific interruption medium within a generator circuit breaker application. The requirements of generator circuit breakers were determined and used to evaluate the interruption mediums in question. To ensure practical results, commonly used layouts were used to determine the effect of using a generator circuit breaker on the reliability, availability and the mean time to repair of a power station electrical distribution layout. Furthermore, the effect of the protection on the generator and generator transformer was evaluated. It was found that increased selectivity of the protection system by using a generator circuit breaker limits the extent of equipment damage in case of failure. Practical layouts were used to determine the effect on reliability. The analysis was conducted using assumed values of operational costs to determine the cost incurred through the change in reliability of the power station. By adding a generator circuit breaker, the station transformer and associated equipment is regarded as back-up or redundant equipment. This increases the reliability of the power station dramatically and limits the risk of income lost due to failures. The full evaluation included the estimation of the capital investment costs and the impact that the additional cost has on the operational requirements of a power station. The study determined that the capital cost required to use a generator circuit breaker results in no additional income for a power station. Through the increased protection, higher availability and the possible omission of power station ancillary equipment, the use of generator circuit breakers will result in more power being delivered and more income generated by a power station. The study proved that the generator circuit breaker is a critical part of a power station layout and is a necessary capital requirement to ensure the sustainability of the power station. / Thesis (M.Ing. (Electrical and Electronic Engineering))--North-West University, Potchefstroom Campus, 2010.

Thesis (M.S.)--Materials Science and Engineering, Georgia Institute of Technology, 2005. / Suresh, Committee Member ; C.P. Wong, Committee Member ; Rao R. Tummala, Committee Chair. Includes bibliographical references.

Th. 3e cycle--Électron.--Grenoble--I.N.P.L., 1983. N°: D3 199.

L’objectif principal du projet est d’étudier les techniques d’analyses de défaillances des circuits intégrés VLSI basées sur l’emploi de laser. Les études ont été effectuées sur l’équipement à balayage laser MERIDIAN (DCGSystems) et le testeur Diamond D10 (Credence) disponible au CNES. Les travaux de thèse concernent l’amélioration des techniques dynamiques dites DLS comme « Dynamic Laser Stimulation ». Les techniques DLS consistent à perturber le fonctionnement d’un circuit intégré défaillant par effet photoélectrique ou effet photothermique, en fonctionnement dynamique, à l’aide d’un faisceau laser continu balayant la surface du circuit. Un faisceau laser modulé avec des impulsions supérieures à la nanoseconde et de façon synchrone avec le test électrique à l’aide d’un signal TTL peut être également avantageusement utilisé pour localiser des défauts non accessibles par des techniques purement statiques (OBIRCh, OBIC etc.). L’analyse de la réponse des paramètres électriques à la perturbation laser conduit à une identification de l’origine de la défaillance dynamique. L’optimisation des techniques DLS actuelles permet d’augmenter le taux de succès des analyses de défaillance et d’apporter des informations difficilement accessibles jusqu’alors, qui permettent la détermination de la cause racine de la défaillance.Dans un premier temps, le travail réalisé a consisté en l’amélioration du processus d’analyse des techniques DLS par l’intégration étroite avec le test de façon à observer tout paramètre électrique significatif lors du test DLS. Ainsi, les techniques de « Pass-Fail Mapping » ou encore les techniques paramétriques de localisation de défauts ont été implémentées sur le banc de test constitué du Meridian et du D10. La synchronisation du déroulement du test opéré par le testeur avec le balayage laser a permis par la suite d’établir des méthodologies visant à rajouter une information temporelle aux informations spatiales. En effet, en utilisant un laser modulé nous avons montré que nous étions capable d’identifier avec précision quels sont les vecteurs impliqués dans le comportement défaillant en modulant l’éclairement du faisceau laser en fonction de la partie de la séquence de test déroulée. Ainsi nous somme capable de corréler la fonction défaillante et les structures du CI impliquées. Cette technique utilisant le laser modulé est appelée F-DLS pour « Full Dynamic Laser Stimulation ». A l’inverse, nous pouvons connaitre la séquence de test qui pose problème, et par contre ne pas connaitre les structures du CI impliquées. Dans l’optique de rajouter cette l’information, il a été développé une technique de mesure de courant dynamique. Cette technique s’est avérée efficace pour obtenir des informations sur le comportement interne du CI. A titre d’exemple, prenons le cas des composants « latchés » où les signaux sont resynchronisés avant la sortie du composant. Il est difficile, même avec les techniques DLS actuelles, d’avoir des informations sur une dérive temporelle des signaux. Cependant l’activité interne du composant peut être caractérisée en suivant sur un oscilloscope l’évolution du courant lorsque le circuit est actif, sous la stimulation laser. L’information sur la dérive temporelle peut être extraite par observation de cette activité interne.Enfin, ces techniques de stimulation laser dynamique, ont également prouvé leur efficacité pour l’étude de la fiabilité des CI. La capacité de ces techniques à détecter en avance d’infimes variations des valeurs des paramètres opérationnels permet de mettre en évidence l’évolution des marges de ces paramètres lors d’un processus de vieillissement accéléré. L’étude de l’évolution de la robustesse des CI face aux perturbations externes est un atout majeur qu’apportent les techniques DLS à la fiabilité.Les méthodologies développées dans cette thèse, sont intégrées dans les processus d’analyse et de caractérisation de CI au laboratoire. / The principal objective of the project is to investigate laser based techniques for failure analysis of VLSI integrated circuits. The investigations will be performed on the DCGSystems’ Meridian laser scanning microscope coupled with the Credence’s Diamond D10 tester available at CNES. This study was interested more specifically in the improvement of dynamic laser stimulation techniques said DLS like Dynamic Laser Stimulation. DLS techniques consists in modifying the operation of a dynamically failing integrated circuit by photoelectric effect or photothermal effect using a continuous laser beam sweeping the surface of the circuit. A laser beam modulated in the nanosecond range synchronously with the electrical test through a TTL signal can also be advantageously used. Analysis of the electrical parameters response to the laser disturbance leads to an identification of the dynamic failure origin. The optimization of current DLS techniques will increase the failure analyses success rate and bring information hardly accessible by other means, which allows determining the failure root cause. The work performed was the improvement of the DLS process flow by closely integrating the test to monitor any relevant electrical parameters upon DLS. The « Pass-Fail Mapping » technique and the parametric techniques were implemented on the test tools combining the D10 and the Meridian. The synchronization of the test with the laser scan allows establishing methodologies and techniques in order to add timing information to the defect localisation. Indeed, by modulating the laser beam depending on the test pattern sequences, we show our capability to identify precisely which are the vectors responsible for the IC defective behaviour. We are able now to correlate the defective IC functions with the IC structures involved. This technique is known as F-DLS for Full Dynamic Laser Stimulation.In some cases, we know when the failure occurs in the test pattern but we ignore which IC structures are involved. So, we also developed a dynamic current measurement under laser stimulation technique. This technique proved to be efficient to obtain information about the internal IC behaviour. As an example, for the latched component which signals are synchronised just before the outputs, it is hard to measure shift in the signal propagation. Nevertheless, the IC internal activities can be characterized by monitoring on a scope the current variations under laser stimulation when the IC is activated. The information about the shift in the signal propagation could be extracted then by observing of the IC internal activities.Finally, these DLS techniques proved their efficiency for device qualification for reliability issues. Their accuracy allows early detection of operational parameter tiny variations. This is used to highlight electrical parameter margin evolutions during accelerated aging process. DLS techniques demonstrate their potential to deal with the IC robustness evolution facing external perturbation for reliability purposes.The techniques and methodologies developed during this work have been successfully integrated in the IC analysis and characterisation process in the laboratory. We exposed these techniques but the main case studies remain confidential.

Call number: LD2668 .T4 1964 H91 / Master of Science