Global ETD Search

81	Canonic active RC networks Aikens, Richard Stanley, 1936- January 1972 (has links) No description available. Electronic circuit design.
82	Overload protection using solid state devices Means, James Andrew, 1937- January 1966 (has links) No description available. Electric circuit-breakers.
83	A fast circuit similarity-based placement engine for field programmable gate arrays Shi, Xiaoyu Unknown Date No description available. FPGA Circuit similarity Placement
84	Opportunities and limitations of three-dimensional integration for interconnect design Joyner, James W. 08 1900 (has links) No description available.
85	Computer-aided-design of metal-oxide semiconductor circuitry using a process-sensitive device model Parker, Richard Frederick 12 1900 (has links) No description available. Semiconductors Electronic circuit design
86	A flexible approach to mask-level VLSI routing Sharpe, M. F. January 1990 (has links) No description available. 621.3192 Integrated circuit design
87	A gate matrix approach to VLSI logic layout Gani, Sohail M. January 1990 (has links) No description available. 621.31042 Integrated circuit design
88	A high-level design interface for analogue silicon compilation Winder, C. L. January 1989 (has links) No description available. 621.3994 Integrated circuit design
89	Rapid synchronization techniques for direct sequence spread spectrum systems Chreitah, B. January 1985 (has links) No description available. 621.382 Communications/circuit design
90	Fault-tolerant hardware designs and their reliability analysis Hafezparast, Mahmoud January 1990 (has links) Fault-tolerance, which is a complement to fault prevention, is an effective method of achieving ultra-high reliability. By taking this approach fault free computation can be achieved despite the presence of fault in the system. In this thesis three new fault tolerant techniques are presented and their advantages over well known fault-tolerant strategies are shown. One of these new techniques achieves higher reliability than any other similar techniques presented in the literature. Generally fault-tolerant structures consist of four major blocks: the replicated modules, the disagreement and detection circuit, the switching circuit, and the voting mechanism. The most critical component in a fault-tolerant system is the voter because the final output of the system is computed by this component. This dissertation presents a new implementation for voters which reduces both the complexity and the occupied area on the chip. The structures of the three techniques developed in this work are such that the complexity of their switching mechanisms grows only linearly with the number of modules but the voting mechanism complexity increases significantly. This is a better approach than those schemes in which the switching complexity increases significantly and the voter's complexity remains constant or grows linearly with the number of modules because it is easier to implement a complex voter than a complex switch (voters have more regular structures). Extensive comparisons are made between different fault-tolerant techniques. A new reliability model is also developed for system reliability evaluation of the new designs. The results of these analyses are plotted, and the advantages of the new techniques are demonstrated. In the final part of the work an expert system is described which uses the knowledge acquired by these comparisons. This expert system is meant as a prototype of a component of a CAD tool which will act as an advisor on fault-tolerant techniques. 621.31042 Integrated circuit reliability

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