Good failure analysis is the ability to determine the site of a circuit defect quickly and accurately. We propose a method for defect site prediction that is based on a site's probability of excitation, making no assumptions about the type of defect being analyzed. We do this by analyzing fault signatures and comparing them to the defect signature. We use this information to construct an ordered list of sites that are likely to be the site of the defect.

Improving the performance and functionality of contemporary debugging tools is essential to alleviate the debugging task. This dissertation aims at narrowing the gap between current capabilities of debugging tools and industry requirements by improving two important debugging techniques: error trace compaction and automated debugging. Error trace compaction leverages incremental SAT and heuristics to reduce the number of clock cycles required to observe a failure in an error trace. The technique presented reduces the length of the error trace to a minimum while improving performance by 8× compared to a previous technique. The second contribution uses maximum satisfiability to enhance the functionality and performance of automated debuggers. The method proposed can identify where in the design the bug is located and when in the error trace the bug is excited. Compared to a competitive SAT-based approach, our formulation produces problems that are 80% smaller and that can be solved 4.5x faster.

Improving the performance and functionality of contemporary debugging tools is essential to alleviate the debugging task. This dissertation aims at narrowing the gap between current capabilities of debugging tools and industry requirements by improving two important debugging techniques: error trace compaction and automated debugging. Error trace compaction leverages incremental SAT and heuristics to reduce the number of clock cycles required to observe a failure in an error trace. The technique presented reduces the length of the error trace to a minimum while improving performance by 8× compared to a previous technique. The second contribution uses maximum satisfiability to enhance the functionality and performance of automated debuggers. The method proposed can identify where in the design the bug is located and when in the error trace the bug is excited. Compared to a competitive SAT-based approach, our formulation produces problems that are 80% smaller and that can be solved 4.5x faster.

The in-circuit emulator (ICE) is commonly adopted as a microprocessor debugging technique which features many advantages, such as low demand for hardware and repeatable use of the pins on the JTAG port. The development of system-on-chip technology has matured significantly in recent years. The microprocessors in system-on-chip designs have been applied in a variety of ways, and different microprocessors are being used in the embedded system. The traditional modus operandi of debug control, in which an ad hoc hardware/software package is required for each microprocessor, is not economical as far as programming and designing are concerned. Thus it is advisable to design a more flexible debug control hardware/software package which can fit into different embedded microprocessors with in-circuit emulators. This thesis reviews several types of embedded in-circuit emulator structure and comes up with a parameterized, modularized hardware/software package for controlling in-circuit emulators. An initial analysis of microprocessor systems and embedded debug circuits helps us to elicit reusable parameters so that we can achieve our desired debug control by simply adjusting parameters when we work on different microprocessor architectures and embedded debug circuits. An ensuing examination of the reusability and functionality of our designed debug control hardware/software enables us to group all the functions of our hardware/software package into different functional modules so that we can simply replace relevant functional modules on different microprocessor architectures and embedded debug circuits. The parameterized design allows us to use a single debug control software program on different microprocessor systems with the slightest change of parameter setting. The modularized model has the merit of minimizing our effort of debug control through module replacement when we need to adapt our software to a new environment (as when we want to use it on a different operating system or when we want to apply it to a different communication interface).

Our investigation was to study the feasibility of piece-wise synchronization of chaotic circuits. In conventional experiments of electronic-circuit chaotic synchronization, two circuits were real-time and continuous connected together. In our research, a computer was used as the master subsystem that output chaotic signals to a slave circuit to study the performance of synchronization. The circuit was based on Cuomo¡¦s design. Several methods of piece-wise control were tested to find out the key point of chaotic synchronization. The experimental results revealed that the most important synchronized waveforms were the chaotic orbits near the region that the attractor change quadrants. A conditional piece-wise synchronization method was developed based on our discoveries. Comparing to the periodic piece-wise synchronization method, our method is more robust to sustain the circuit noise. Another advantage is that, in our method, the experimental results fit the computer simulation quite well.

An in-circuit emulator (ICE) is an important tool for the development of microprocessor-based systems. External ICE boxes are complex and expensive piece of hardware so their use is usually limited to debugging phases of the microprocessor-based systems that involve hardware/software integration or investigation of real time I/O or bus events. On the other hand, a ROM monitor is inexpensive, but provides less observablity for the microprocessor¡¦s operations. In either case, the design practice of the ICE devices is usually independent to the design task of the microprocessor itself. The performance and cost of the ICE devices are not relevant to the microprocessors since they are two different entities. The ICE¡¦s are used only during the development/debugging of the microprocessor-based systems by substituting the original microprocessor on the socket with the ICE. The ICE is unplugged after debugging and the original microprocessor is placed back into the socket for normal operations of the microprocessor-based systems. Therefore, the performance and cost of the ICE¡¦s do not impact these of the microprocessor-based systems because the ICE¡¦s do not exist in them. We then define three feasible solutions software, hardware and hybrid) and integrate them with a synthesizable ARM7 icroprocessor core. The microprocessors with the embedded ICE¡¦s are synthesized and simulated to analyze and compare the corresponding hardware/software performance and cost and the debugging features of these approaches.

Thesis (Ph. D.)--University of Texas at Austin, 2002. / Vita. Includes bibliographical references. Available also from UMI Company.

Thesis (Ph. D.)--University of Cincinnati, 2002. / Title from electronic thesis title page (viewed Apr. 21, 2003). Includes abstract. Includes bibliographical references.

This dissertation explores the cost of programmability in computing devices as measured relative to fixed-function devices implementing the same functionality using the same physical fabrication technology. The central claim elevates programmability to an explicit design parameter that (1) can be rigorously defined, (2) has measurable costs amenable to high-level modeling, (3) yields a design-space with distinct regions and properties, and (4) can be usefully manipulated using computer-aided design tools. The first portion of the the work is devoted to laying a rigorous logical foundation to support both this and future work on the subject. The second portion supports the thesis within this established logical foundation, using a specific engineering problem as a narrative vehicle. The engineering problem explored is that of mechanically adding a useful degree of programmability into preexisting fixed-function logic while minimizing the added overhead. Varying criteria for usefulness are proposed and the relative costs estimated both analytically and through case-study using standard-cell logic synthesis. In the case study, a methodology for the automatic generation of reconfigurable logic highly optimized for a specific set of computing applications is demonstrated. The approach stands in contrast to traditional reconfigurable computing techniques which focus on providing general purpose functionality at the expense of substantial overheads relative to fixed-purpose implementations. / text

No description available.