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  • About
  • The Global ETD Search service is a free service for researchers to find electronic theses and dissertations. This service is provided by the Networked Digital Library of Theses and Dissertations.
    Our metadata is collected from universities around the world. If you manage a university/consortium/country archive and want to be added, details can be found on the NDLTD website.

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Showing 21 to 30 of 248 (0.021 seconds)

Spelling suggestions: "subject:"[een] CIRCUIT DESIGN"" "subject:"[enn] CIRCUIT DESIGN""

21

Optimization of regular VLSI structures for silicon compilation

Hallam, Philip January 1990 (has links)
No description available.
620.0042029
VLSI circuit design
22

RF modelling of deep-submicron CMOS and heterojunction bipolar transistor for wireless communication systems

Shah Alam, Huhmmad January 2002 (has links)
No description available.
621
Circuit design
23

Optimum MESFET frequency multiplier design

Tang, Wing Ho Aaron January 1993 (has links)
No description available.
621.3192
Integrated circuit design
24

Circuit techniques for CMOS amplifier accuracy and robustness improvement in high-side current sensing Read-out circuit

Yan, Rong Shen January 2017 (has links)
University of Macau / Faculty of Science and Technology / Department of Electrical and Computer Engineering
Electronic circuit design
25

Sequential logic instrumentation

Hull, William T. January 1964 (has links)
Call number: LD2668 .T4 1964 H91 / Master of Science
Electronic circuit design.
Masters theses
26

The design of distributed amplifiers and mixers

Castelino, A. J. January 1987 (has links)
No description available.
621.3192
Circuit design for amplifiers
27

Techniques and tools for developing Ruby designs

Guo, Shaori January 1997 (has links)
No description available.
621.39
Hardware compilers; Circuit design
28

Circuit Design for Realization of a 16 bit 1MS/s Successive Approximation Register Analog-to-Digital Converter

Brenneman, Cody R. 28 April 2010 (has links)
As the use of digital systems continues to grow, there is an increasing need to convert analog information into the digital domain. Successive Approximation Register (SAR) analog-to-digital converters are used extensively in this regard due to their high resolution, small die area, and moderate conversion speeds. However, capacitor mismatch within the SAR converter is a limiting factor in its accuracy and resolution. Without some form of calibration, a SAR converter can only reasonably achieve an accuracy of 10 bits. The Split-ADC technique is a digital, deterministic, background self-calibration algorithm that can be applied to the SAR converter. This thesis describes the circuit design and physical implementation of a novel 16-bit 1MS/s SAR analog-to-digital converter for use with the Split-ADC calibration algorithm. The system was designed using the Jazz 0.18um CMOS process, successfully operates at 1MS/s, and consumes a die area of 1.2mm2. The calibration algorithm was applied, showing an improvement in the overall accuracy of the converter.
ADC
Circuit design
Calibration
SAR
29

Cost-effective test at system-level

Kim, Hyun-moo, January 2002 (has links)
Thesis (Ph. D.)--University of Texas at Austin, 2002. / Vita. Includes bibliographical references. Available also from UMI Company.
30

Active equivalent network generation and sensitivity study

Price, Burt Lee 05 1900 (has links)
No description available.
Electronic circuit design
Electric networks

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