The objective of this thesis is to design a high speed digital FIR filter. The inputs of the system come from a Delta-Sigma modulator. This FIR filter takes 1024 inputs, multiplies them with their coefficients and adds the results. The main design task is to take the input data, which are unweighted single-bit binary numbers at 156MHz, multiply each bit with the corresponding coefficient and add them to get a weighted multi-bit output at 20MHz. / Graduation date: 1997

Due to advances in high-density low-cost VLSI and communication technology, digital filtering and signal processing are being widely used for real-time signal processing applications. Given the filter specification, choosing the best filter structure for a given application is not a trivial task. The choice of a particular filter structure depends on many factors such as sensitivity to finite word-length quantization effects, hardware complexity and power consumption. The objective of this thesis is to examine digital IIR (Infinite Impulse Response) filter structures for the VLSI implementation of narrow-band sharp-transition filters. This thesis examines several different digital IIR filter structures; namely cascade form IIR filter, five different digital lattice filters and lattice wave digital filter structures. For fixed-point implementation, the sensitivity, round-off noise properties and the scaling of these filter structures are described and analyzed. These filter structures are compared with respect to the architectural complexity, the sensitivity to coefficient quantization, the round-off noise due to product quantization and the signal dynamic range. Fixed-point implementation simulations using two's-complement arithmetic are carried out for a number of narrow-band sharp-transition digital low-pass filters. / Graduation date: 1995

Submitted by Automa??o e Estat?stica (sst@bczm.ufrn.br) on 2017-03-23T16:42:09Z No. of bitstreams: 1 MadsonEulerTavaresPereira_DISSERT.pdf: 17433029 bytes, checksum: 25b2ffcc0d75343e17d9515d89ee6bea (MD5) / Approved for entry into archive by Monica Paiva (monicalpaiva@hotmail.com) on 2017-03-23T16:48:26Z (GMT) No. of bitstreams: 1 MadsonEulerTavaresPereira_DISSERT.pdf: 17433029 bytes, checksum: 25b2ffcc0d75343e17d9515d89ee6bea (MD5) / Made available in DSpace on 2017-03-23T16:48:26Z (GMT). No. of bitstreams: 1 MadsonEulerTavaresPereira_DISSERT.pdf: 17433029 bytes, checksum: 25b2ffcc0d75343e17d9515d89ee6bea (MD5) Previous issue date: 2014-06-26 / Localizada no contexto de uma sociedade tomada pela cibercultura, esta influenciando diretamente as rela??es entre literatura, ilustra??es e novos suportes digitais de leitura, a presente disserta??o se prop?e a pensar as possibilidades do design de comunica??o no universo dos ebooks criados para tablets. Posto isto, o objetivo geral ? descrever e analisar as 26 ilustra??es din?micas interativas digitais da edi??o/vers?o gratuita de ?Alice no Pa?s das Maravilhas?, batizada de ?Alice for the Ipad? pela empresa de produtos eletr?nicos Apple. Optou-se por lan?ar m?o de uma pesquisa qualitativa, multimodal, tendo como fio condutor uma an?lise descritiva dos objetos supracitados,amparada por referenciais te?ricos e cr?ticos constantes na bibliografia do presente estudo. Almeja-se que esta abordagem em espec?fico, possibilite novos di?logos e contribua com as pesquisassobre comunica??o e produ??o de sentido no campo das ilustra??es vinculadas ?s novas tecnologias. / Localizada no contexto de uma sociedade tomada pela cibercultura, esta influenciando diretamente as rela??es entre literatura, ilustra??es e novos suportes digitais de leitura, a presente disserta??o se prop?e a pensar as possibilidades do design de comunica??o no universo dos ebooks criados para tablets. Posto isto, o objetivo geral ? descrever e analisar as 26 ilustra??es din?micas interativas digitais da edi??o/vers?o gratuita de ?Alice no Pa?s das Maravilhas?, batizada de ?Alice for the Ipad? pela empresa de produtos eletr?nicos Apple. Optou-se por lan?ar m?o de uma pesquisa qualitativa, multimodal, tendo como fio condutor uma an?lise descritiva dos objetos supracitados,amparada por referenciais te?ricos e cr?ticos constantes na bibliografia do presente estudo. Almeja-se que esta abordagem em espec?fico, possibilite novos di?logos e contribua com as pesquisassobre comunica??o e produ??o de sentido no campo das ilustra??es vinculadas ?s novas tecnologias.

<p> This thesis describes the development of an ultra low frequency digital analyzer from mathematical concepts and error characteristics set out in a publication^2 co-authored by the supervisor. The development is carried to the actual construction of a practical, economical, operating instrument, capable of giving information leading directly to the mean square value and the approximate amplitude probability distribution for ultra low frequency waveforms, both periodic and non-periodic. The final detailed design is described and justified, and the error characteristics derived in the above mentioned publication are interpreted for the design. No further development of principles or error characteristics is undertaken.</p> / Thesis / Master of Engineering (MEngr)

How form translates as it moves between the physical and the digital has caught my interest. I collect data through different types of 3d scanning exploring a range of technologies. In the digital realm, the information captured presents itself as a messy abstraction to the original where some information is added while other is lost. Developing the material, I adopt complex content aware auto fill algorithms - a strategy that becomes essential for the project.  In my installation visitors can explore thresholds between the real and the virtual. My firm belief is that the traces from the physical and digital wear and tear add value in that they unpack my process, birthing something strange while familiar. / Hur form översätts när den rör sig mellan det fysiska och det digitala har fångat mitt intresse. Jag samlar in data genom olika typer av 3d-skanning och utforskar en rad olika tekniker. I det digitala rummet redovisas den dokumenterade datan som en rörig abstraktion till sitt original, där viss information adderas medan annan förloras. Jag antar i min designprocess komplexa content aware auto fill-algoritmer - en strategi som blir central för projektet. I min installation bjuds besökare att utforska möten mellan det verkliga och det virtuella. Det är min övertygelse att spåren från det fysiska och det digitala slitaget adderar mervärden genom att de packar upp min process samtidigt som något märkligt men bekant materialiseras.

A new structure for the implementation of bit/serial adaptive IIR filter is presented. The bit level system consists of gated full adders for the arithmetic unit and data latches for the data path. This approach allows recursive operation of the IIR filter to be implemented without any global interconnections, minimal delay time, chip area and I/O pins. The coefficients of the filter can be updated serially in real time for time invariant and adaptive filtering. A fourth order bit/serial IIR filter is implemented on a 2 micron CMOS technology clocked at 55 MHz. / Graduation date: 1992

No description available.

AN ABSTRACT OF THE THESIS OF Zeeshan Ahmed Bashir, for the Masters of Science degree in Electrical and Computer Engineering, presented on 29th June 2015, at Southern Illinois University Carbondale TITLE: MSB FIRST ARITHMETIC CIRCUIT FOR MOTION ESTIMATION MAJOR PROFESSOR: Dr. Haibo Wang This thesis presents a novel design of arithmetic circuits that perform computation from MSB to LSB in a serial manner. In the MSB first serial computation, the result is gradually refined along the computation cycles. If the result is used to do a comparison with a threshold, such as in motion estimation applications, it is possible to draw the comparison conclusion in the middle of the computation and subsequently skip the rest of the computation. Thus the MSB-first serial computation potentially results in significant power reduction, making them attractive to low power applications. Unlike the existing MSB-first design that uses redundant number system, the proposed design is based on the widely used 2’ complementary number system, making the proposed circuits more compact and consuming less power as compared to the existing circuits that use signed digital bit numbers. The proposed arithmetic circuits have been used to implement variable block size motion estimation (VBSME) circuits, including block sizes of 4x4, 8x4, 8x8, 8x16 and 16x16 on a Xilinx Spartan 6 FPGA device. The performance of the proposed design is compared with the design based on existing MSB-first arithmetic circuit. The comparison shows the proposed design consumes significantly less power compared to the reference design.

abstract: Parts are always manufactured with deviations from their nominal geometry due to many reasons such as inherent inaccuracies in the machine tools and environmental conditions. It is a designer job to devise a proper tolerance scheme to allow reasonable freedom to a manufacturer for imperfections without compromising performance. It takes years of experience and strong practical knowledge of the device function, manufacturing process and GD&T standards for a designer to create a good tolerance scheme. There is almost no theoretical resource to help designers in GD&T synthesis. As a result, designers often create inconsistent and incomplete tolerance schemes that lead to high assembly scrap rates. Auto-Tolerancing project was started in the Design Automation Lab (DAL) to investigate the degree to which tolerance synthesis can be automated. Tolerance synthesis includes tolerance schema generation (sans tolerance values) and tolerance value allocation. This thesis aims to address the tolerance schema generation. To develop an automated tolerance schema synthesis toolset, to-be-toleranced features need to be identified, required tolerance types should be determined, a scheme for computer representation of the GD&T information need to be developed, sequence of control should be identified, and a procedure for creating datum reference frames (DRFs) should be developed. The first three steps define the architecture of the tolerance schema generation module while the last two steps setup a base to create a proper tolerance scheme with the help of GD&T good practice rules obtained from experts. The GD&T scheme recommended by this module is used by the tolerance value allocation/analysis module to complete the process of automated tolerance synthesis. Various test cases are studied to verify the suitability of this module. The results show that software-generated schemas are proper enough to address the assemblability issues (first order tolerancing). Since this novel technology is at its initial stage of development, performing further researches and case studies will definitely help to improve the software for making more comprehensive tolerance schemas that cover design intent (second order tolerancing) and cost optimization (third order tolerancing). / Dissertation/Thesis / Masters Thesis Mechanical Engineering 2016

No description available.