The solutions to many problems in structural design and analysis are quite laborious and time-consuming. This fact has motivated the search for analogies that might lead to quicker, yet accurate solutions. Fortunately, the laws governing structural behavior find many parallels among the laws of electricity and, therefore, it is conceivable that electrical circuits may be devised which are equivalent to certain structural problems. It is the purpose of this thesis to set up several equivalent circuits and to present solutions using accepted methods of analysis. Only statistical loadings are considered. Information about necessary equipment for experimental work is given. Examples given show which analogs are best suited to certain structural problems. It is hoped that the foregoing will stimulate more investigation in the field of electrical analogies for structural problems. A discussion follows which will present the work which has previously been done in this field. This will help to acquaint the reader with the subject and show the need for further development. / Master of Science

The single-phase rectifier filter circuits, including the half- and full-wave rectifiers with a capacitor and full-wave rectification with either a series inductor or a choke-input filter, have been analyzed taking into account the voltage drop across the tube and the transformer. In these analyses the high-vacuum thermionic diode was considered. The voltage-current characteristic curve of a diode was assumed linear, and the equivalent resistance of the tube was chosen equal to the reciprocal of the slope of the diode characteristic curve in the conducting region. For the capacitive filtering case, the equations expressing the ignition angle, the extinction angle, and the ratio of the d-c output voltage to the peak value of the applied voltage when the steady state condition is reached have been derived. It was found that these equations not only depend upon the product of the angular frequency of the applied voltage and the time constant of load circuit, but also depend on the ratio of the load resistance to the equivalent resistance of the tube and the source transformer. Most of these equations appear to be of a transcendental form, the solution of which requires either graphical or trial-and-error method. Both of these require tedious work and are time consuming with hand computations. However it is easily accomplished today by the use of an IBM 7040 computer. The calculated curves showing the variation of the ignition angle, the extinction angle, and the ratio of the d-c output voltage to the peak value of the supply-voltage for half- and full-wave rectifications were plotted with wRC as abcissa for several different values of the ratio of the load resistance to the equivalent resistance of tube and transformer. The equations derived for the direct output voltage of the rectifier circuit with either the series inductor or the choke-input filters show that they depend only on the ratio of the load resistance to the total resistance of the tube, the transformer, and the inductor. All the equations mentioned above had been experimentally verified. It is found that the calculated results checked closely with the experimental data if the equivalent resistances were properly chosen. The effect of circuit parameters on the behavior of rectifier circuits operated with three types of filters have been discussed. It becomes evident that the tube and the transformer resistance of practical circuits appears as an additional parameter which cannot be neglected in t4e analysis of the single-phase rectifier. However, inclusion of this resistance greatly complicates the analysis. The method of analysis presented in this paper may be extended to other types of rectifier circuits. Although the analysis made in this paper did not take into account all of the possible factors which may be involved in the practical circuits, nevertheless the results were presented in convenient form for practical use. / M.S.

Thesis (M.S.)--University of Texas at El Paso, 2005. / Title from title screen. Vita. CD-ROM. Includes bibliographical references. Also available online.

It was the purpose of this investigation to study the effect of varying the direct to reverse time ratio of periodically reversed direct current from 1.0 to 20.0 on the electrolytic production of lead chromate at an average anode current density of 0.0059 amperes per square centimeter, and to study the effect of 60 and 502.3 ± 7.7 cycles per second from 0.00113 to 0.01546 amperes per square centimeter of peak superimposed alternating current on direct current on the yield of lead chromate prepared by the electrolysis of a bath containing potassium chromate and sodium nitrate between lead electrodes. Electrolysis of a bath containing 3.60 grams of potassium chromate, 11.62 grams of sodium nitrate, end 1000 grams of water with simple direct current yielded 6.07 grams of lead chromate per ampere-hour, the purity being 92.7 percent lead chromate. The anode current density was 0.0049 amperes per square centimeter, and the current efficiency was 98.1 percent. During the electrolysis, by maintaining the ph of the electrolyte at 6.0, by adding a solution to 2.0 weight percent chromic acid, the purity of the product was increased. Electrolysis of the same bath using periodically reversed direct current yielded 4.53 grams of lead chromate per ampere-hour, the purity being 93.9 percent lead chromate. The time ratio was 20.0, the anode current density was 0.0049 amperes per square centimeter, and the current efficiency was 66.75 percent. Decreasing the direct to reverse time ratio gave lower yields and purities. Apparently, there is no advantage in using periodically reversed direct current over the use of direct current for this reaction under the above conditions. Electrolysis of the same bath with alternating current superimposed on direct current yielded 5.49 grams of lead chromate per direct current ampere-hour, at a purity of 99.4 percent lead chromate, when using 494.7 cycle alternating current. The alternating and direct current densities were 0.0078 and 0.0048 amperes per square centimeter, respectively. This was the purest product obtained in this investigation. Use of 60 cycle alternating current yielded 3.83 grams of lead chromate per direct current ampere-hour, at a purity of 93.9 percent lead chromate. The alternating and direct current densities were 0.00141 and 0.00484 amperes per square centimeter. Further experiments were made using direct current and periodically reversed direct current on a bath containing 6.80 grams of potassium chromate, 8.14 grams of sodium nitrate, and 1000 grams of water. Results from these electrolytes were much poorer than those obtained with the previous bath, so no experiments with superimposed alternating current on direct current were carried out with this latter bath. / Master of Science

Αυτή η εργασία έχει σαν αντικείμενο την μελέτη των βαθμίδων εισόδου τελεστικών ενισχυτών με εύρος rail-to-rail καθώς και των βαθμίδων εξόδου τάξεως ΑΒ. Μια rail-to-rail βαθμίδα εισόδου, μπορεί να διαχειριστεί την τάση τροφοδοσίας στο έπακρο δεχόμενη σήματα μεγάλου εύρους τάσεων, ενώ η βαθμίδα εξόδου έχει σαν κύριο πλεονέκτημα την γρηγορότερη οδήγηση μεγάλων φορτίων με ελαχιστοποίηση της παραμόρφωσης. Έτσι, στο πρώτο κεφάλαιο παρουσιάζονται οι βασικές αρχές που διέπουν τα κυκλώματα χαμηλής τροφοδοσίας και οι περιορισμοί που πρέπει να ληφθούν υπ’ όψιν κατά τον σχεδιασμό των κυκλωμάτων. Στο δεύτερο κεφάλαιο αυτής της εργασίας παρουσιάζονται οι βασικές αρχές λειτουργίας των rail-to-rail βαθμίδων εισόδου και οι βασικές τεχνικές υλοποίησής τους. Στο τρίτο κεφάλαιο παρουσιάζονται οι βασικές αρχές λειτουργίας των βαθμίδων εξόδου τάξεως ΑΒ με τις αντίστοιχες τεχνικές υλοποίησης. Στα επόμενα κεφάλαια αυτού του συγγράμματος προτείνεται ένας νέος τελεστικός ενισχυτής ο οποίος αποτελείται από μια rail-to-rail βαθμίδα εισόδου και από μία βαθμίδα εξόδου τάξεως ΑΒ ενώ γίνεται χρήση 1V για την τάση τροφοδοσίας. Άλλο ένα πλεονέκτημα της προτεινόμενης αρχιτεκτονικής, είναι αυτό της δυνατότητας ρύθμισης των συνθηκών πόλωσης ώστε να διατηρείται η λειτουργικότητα του ενισχυτή αλλά και να προσαρμόζεται στις εκάστοτε ανάγκες της κάθε εφαρμογής. Πιο συγκεκριμένα ένα από τα πλεονεκτήματα αυτού του τελεστικού ενισχυτή, είναι η δυνατότητα ρύθμισης της διαγωγιμότητας της εισόδου με γραμμικό τρόπο μέσω μιας πηγής ρεύματος. Αντίστοιχα, επιλέγοντας μεγαλύτερο ρεύμα για την βαθμίδα εξόδου υπάρχει η δυνατότητα μείωσης της καθυστέρησης μετάδοσης του σήματος σε μεγάλα φορτία. / -

published_or_final_version / Electrical Engineering / Master / Master of Science in Engineering

This dissertation describes an innovative approach to the state justification portion of the sequential circuit automatic test pattern generation (ATPG) process. Given the absence of a stored fault an ATPG controller invokes some combinational circuit test generation procedure, such as the D-algorithm, to identify a circuit state (goal state) and input vectors that will sensitize a selected fault. The state justification phase then finds a transfer sequence to the goal from the present state. A forward fault propogation search can be successfully guided through state space from the present state but the forward justification search is less efficient and the failure rate is high. The backward function level search invokes inverse RTL level primitives and exploits easy movement of data vectors in structured VLSI circuits. Examples illustrated are in AHPL. This search is equally applicable to an RTL level subset of VHDL. Combinational logic units are treated as functions and the circuit states are partitioned into control states and data states. The search proceeds backwards over the control state space starting from the goal state node and data states are transformed according to the control flow. Vectorized data paths in VLSI circuits and search guiding heuristics which favor convenient inverse functions keep the number of search nodes low. Partial covers, conceptually similar to singular covers in D-algorithm, model the inverse functions of combinational logic units. The search successfully terminates when a child state node logically matches the present state and the present state values can satisfy all the constraints encountered along the search path.

Orientador: Helmo Kelis Morales Paredes / Banca: Sigmar Maurer Deckmann / Banca: Fernando Pinhabel Marafão / Resumo: O presente trabalho aborda o assunto da atribuição de responsabilidades em circuitos elétricos monofásicos com características de baixa tensão (baixo nível de curto circuito). Nesse cenário, o avanço das cargas eletrônicas e das fontes chaveadas propiciou um ambiente na qual tensão e corrente carregam alto conteúdo harmônico desfavorecendo, de certa forma, a Qualidade da Energia Elétrica (QEE). Nesse contexto, o objetivo do trabalho é estudar o comportamento de cargas lineares e não lineares e traçar conclusões a respeito de atribuição de responsabilidades. Para tanto, utilizouse a Teoria da Potência Conservativa (CPT) (do inglês, Conservation Power Theory) que é um modelo matemático para análise de circuitos elétricos sob condições senoidais e não seniodais. Além disso, a CPT permite expandir a análise do problema proposto através de uma Metodologia de Atribuição de Responsabilidades que leva em consideração um circuito equivalente com as informações da impedância de linha (equivalente Thévenin da rede visto pelo PAC) e dos parâmetros equivalentes da carga, mostrando um diferencial frente às metodologias estudadas. Para tanto, um circuito elétrico composto por diferentes cargas lineares e não lineares foi proposto e se pode estudar e discutir o compartilhamento de responsabilidades, buscando respostas acerca das quais parcelas de potência devem ser apontadas às cargas geradoras dos distúrbios harmônicos. A caracterização de cargas e estimação de impedância de linha apresentam resultados bastante satisfatórios. Assim, a metodologia de atribuição de responsabilidades sugere que a potência ativa fundamental deveria ser de responsabilidade das cargas, uma vez que ela representa de fato o fluxo de potência da fonte de alimentação para a carga. Além disso, o trabalho mostrou a fragilidade da PRODIST frente à norma IEEE em relação aos níveis de distorção harmônica de tensão no PAC... / Abstract: This work, aims to the study of the accountability problem focused on single-phase circuits with low voltage characteristics (low level of short circuit). In this scenario, the advancement of electronic loads and switchin devices have promoted and environment in which voltages and currents present high harmonic content, reducing the electrical power quality. In this context, the objective of this work is to study the behavior of linear and nonlinear loads and draw conclusions on accountability in electrical grids, i.e., responsibility in the harmonic content generation. For this purpose, it was applied the Conservative Power Theory (CPT) which is a mathematical tool for electrical circuits analysis on both sinusoidal and nonsinusoidal conditions. Furthermore, the CPT allows the application of a Accontability Methodology that takes into account information of the line impedance (equivalent Thévenin viewed by point of common coupling) and the equivalent parameters of the load. These two considerations represent a differential in relation to the studied methodologies. So, an electrical circuit containing linear and non-linear loads was proposed, and the Accountability Methodology was studied and discussed, seeking answers about the power portions that should be accontable to the harmonic loads. The load characterization and the impedance estimation presented satisfactory results. Then, the Accontability Methodology proposes that the fundamental active power should be accontable to the loads, since it represents the power portion that really flows the power source to the load. In addition, the work showed the fragility of PRODIST in relation to the IEEE standard concerning the harmonic voltage distortion established limits at the point of common coupling / Mestre

High performance computing is critical for the needs of scientific discovery and economic competitiveness. An extreme-scale computing system at 1000x the performance of today’s petaflop machines will exhibit massive parallelism on multiple vertical fronts, from thousands of computational units on a single processor to thousands of processors in a single data center. To facilitate such a massively-parallel extreme-scale computing, a key challenge is power. The challenge is not power associated with base computation but rather the problem of transporting data from one chip to another at high enough rates. This thesis presents architectures and techniques to achieve low power and area footprint while achieving high data rates in a dense very-short reach (VSR) chip-to-chip (C2C) communication network. High-speed serial communication operating at ultra-low supplies improves the energy-efficiency and lowers the power envelop of a system doing an exaflop of loops. One focus area of this thesis is clock synthesis for such energy-efficient interconnect applications operating at high speeds and ultra-low supplies. A sub-integer clockfrequency synthesizer is presented that incorporates a multi-phase injection-locked ring-oscillator-based prescaler for operation at an ultra-low supply voltage of 0.5V, phase-switching based programmable division for sub-integer clock-frequency synthesis, and automatic calibration to ensure injection lock. A record speed of 9GHz has been demonstrated at 0.5V in 45nm SOI CMOS. It consumes 3.5mW of power at 9.12GHz and 0.05𝑚𝑚2 of area, while showing an output phase noise of -100dBc/Hz at 1MHz offset and RMS jitter of 325fs; it achieves a net 𝐹𝑂𝑀𝐴 of -186.5 in a 45-nm SOI CMOS process. This thesis also describes a receiver with a reference-less clocking architecture for high-density VSR-C2C links. This architecture simplifies clock-tree planning in dense extreme-scaling computing environments and has high-bandwidth CDR to enable SSC for suppressing EMI and to mitigate TX jitter requirements. It features clock-less DFE and a high-bandwidth CDR based on master-slave ILOs for phase generation/rotation. The RX is implemented in 14nm CMOS and characterized at 19Gb/s. It is 1.5x faster that previous reference-less embedded-oscillator based designs with greater than 100MHz jitter tolerance bandwidth and recovers error-free data over VSR-C2C channels. It achieves a power-efficiency of 2.9pJ/b while recovering error-free data (BER< 10−12) across a 15dB loss channel. The jitter tolerance BW of the receiver is > 200MHz and the INL of the ILO-based phase-rotator (32- Steps/UI) is <1-LSB. Lastly, this thesis develops a time-domain delay-based modeling of injection locking to describe injection-locking phenomena in nonharmonic oscillators. The model is used to predict the locking bandwidth, and the locking dynamics of the locked oscillator. The model predictions are verified against simulations and measurements of a four-stage differential ring oscillator. The model is further used to predict the injection-locking behavior of a single-ended CMOS inverter based ring oscillator, the lock range of a multi-phase injection-locked ring-oscillator-based prescaler, as well as the dynamics of tracking injection phase perturbations in injection-locked masterslave oscillators; demonstrating its versatility in application to any nonharmonic oscillator.

Next-generation wireless communication systems put more stringent performance requirements on the wireless RF receiver circuits. Sensitivity, linearity, bandwidth and power consumption are some of the most important specifications that often face tightly coupled tradeoffs between them. To increase the data throughput, a large number of fragmented spectrums are being introduced to the wireless communication standards. Carrier aggregation technology needs concurrent communication across several non-contiguous frequency bands, which results in a rapidly growing number of band combinations. Supporting all the frequency bands and their aggregation combinations increases the complexity of the RF receivers. Highly flexible software defined radio (SDR) is a promising technology to address these applications scenarios with lower complexity by relaxing the specifications of the RF filters or eliminating them. However, there are still many technology challenges with both the receiver architecture and the circuit implementations. The performance requirements of the receivers can also vary across different application scenario and RF environments. Field-programmable dynamic performance tradeoff can potentially reduce the power consumption of the receiver. In this dissertation, we address the performance enhancement challenges in the wideband SDRs by innovations at both the circuit building block level and the receiver architecture level. A series of research projects are conducted to push the state-of-the-art performance envelope and add features such as field-programmable performance tradeoff and concurrent reception. The projects originate from the concept of thermal noise canceling techniques and further enhance the RF performance and add features for more capable SDR receivers. Four generations of prototype LNA or receiver chips are designed, and each of them pushes at least one aspect of the RF performance such as bandwidth, linearity, and NF. A noise-canceling distributed LNA breaks the tradeoff between NF and RF bandwidth by introducing microwave circuit techniques from the distributed amplifiers. The LNA architecture uniquely provides ultra high bandwidth and low NF at low frequencies. A family of field-programmable LNA realized field-programmable performance tradeoff with current-reuse programmable transconductance cells. Interferer-reflecting loops can be applied around the LNAs to improve their input linearity by rejecting the out-of-band interferers with a wideband low in- put impedance. A low noise transconductance amplifier (LNTA) that operates in class-AB-C is invented to can handle rail-to-rail out-of-band blocker without saturation. Class-AB and class-C transconductors form a composite amplifier to increase the linear range of the input voltage. A new antenna interface named frequency-translational quadrature-hybrid (FTQH) breaks the input impedance matching requirement of the LNAs by introducing quadrature hybrid couplers to the CMOS RFIC design. The FTQH receiver achieves wideband sub-1dB NF and supports scalable massive frequency-agile concurrent reception.