Thesis (Ph. D.)--Virginia Polytechnic Institute and State University, 1993. / Vita. Abstract. Includes bibliographical references (leaves 115-121). Also available via the Internet.

by Shankar Sastry. / "September 1982." / Bibliography: p. 37-38. / Air Force Office of Scientific Research grant AFOSR-82-0258

This thesis is concerned with the synthesis of passive networks, motivated by the recent invention of a new mechanical component, the inerter, which establishes a direct analogy between mechanical and electrical networks. We investigate the minimum numbers of inductors, capacitors and resistors required to synthesise a given impedance, with a particular focus on transformerless network synthesis. The conclusions of this thesis are relevant to the design of compact and cost-effective mechanical and electrical networks for a broad range of applications. In Part 1, we unify the Laplace-domain and phasor approach to the analysis of transformerless networks, using the framework of the behavioural approach. We show that the autonomous part of any driving-point trajectory of a transformerless network decays to zero as time passes. We then consider the trajectories of a transformerless network, which describe the permissible currents and voltages in the elements and at the driving-point terminals. We show that the autonomous part of any trajectory of a transformerless network is bounded into the future, but need not decay to zero. We then show that the value of the network's impedance at a particular point in the closed right half plane can be determined by finding a special type of network trajectory. In Part 2, we establish lower bounds on the numbers of inductors and capacitors required to realise a given impedance. These lower bounds are expressed in terms of the extended Cauchy index for the impedance, a property defined in that part. Explicit algebraic conditions are also stated in terms of a Sylvester and a Bezoutian matrix. The lower bounds are generalised to multi-port networks. Also, a connection is established with continued fraction expansions, with implications for network synthesis. In Part 3, we first present four procedures for the realisation of a general impedance with a transformerless network. These include two known procedures, the Bott-Duffin procedure and the Reza-Pantell-Fialkow-Gerst simplification, and two new procedures. We then show that the networks produced by the Bott-Duffin procedure, and one of our new alternatives, contain the least possible number of reactive elements (inductors and capacitors) and resistors, for the realisation of a certain type of impedance (called a biquadratic minimum function), among all series-parallel networks. Moreover, we show that these procedures produce the only series-parallel networks which contain exactly six reactive elements and two resistors and realise a biquadratic minimum function. We further show that the networks produced by the Reza-Pantell-Fialkow-Gerst simplification, and the second of our new alternatives, contain the least possible number of reactive elements and resistors for the realisation of almost all biquadratic minimum functions among the class of transformerless networks. We group the networks obtained by these two procedures into two quartets, and we show that these are the only quartets of transformerless networks which contain exactly five reactive elements and two resistors and realise all of the biquadratic minimum functions. Finally, we investigate the minimum number of reactive elements required to realise certain impedances, of greater complexity than the biquadratic minimum function, with series-parallel networks.

Made available in DSpace on 2016-03-07T19:21:00Z (GMT). No. of bitstreams: 0 Previous issue date: 2015-11-05. Added 1 bitstream(s) on 2016-03-07T19:24:55Z : No. of bitstreams: 1 000858966.pdf: 2028080 bytes, checksum: dac7a5c9d241c31e2066c270e8e6f473 (MD5) / O presente trabalho aborda o assunto da atribuição de responsabilidades em circuitos elétricos monofásicos com características de baixa tensão (baixo nível de curto circuito). Nesse cenário, o avanço das cargas eletrônicas e das fontes chaveadas propiciou um ambiente na qual tensão e corrente carregam alto conteúdo harmônico desfavorecendo, de certa forma, a Qualidade da Energia Elétrica (QEE). Nesse contexto, o objetivo do trabalho é estudar o comportamento de cargas lineares e não lineares e traçar conclusões a respeito de atribuição de responsabilidades. Para tanto, utilizouse a Teoria da Potência Conservativa (CPT) (do inglês, Conservation Power Theory) que é um modelo matemático para análise de circuitos elétricos sob condições senoidais e não seniodais. Além disso, a CPT permite expandir a análise do problema proposto através de uma Metodologia de Atribuição de Responsabilidades que leva em consideração um circuito equivalente com as informações da impedância de linha (equivalente Thévenin da rede visto pelo PAC) e dos parâmetros equivalentes da carga, mostrando um diferencial frente às metodologias estudadas. Para tanto, um circuito elétrico composto por diferentes cargas lineares e não lineares foi proposto e se pode estudar e discutir o compartilhamento de responsabilidades, buscando respostas acerca das quais parcelas de potência devem ser apontadas às cargas geradoras dos distúrbios harmônicos. A caracterização de cargas e estimação de impedância de linha apresentam resultados bastante satisfatórios. Assim, a metodologia de atribuição de responsabilidades sugere que a potência ativa fundamental deveria ser de responsabilidade das cargas, uma vez que ela representa de fato o fluxo de potência da fonte de alimentação para a carga. Além disso, o trabalho mostrou a fragilidade da PRODIST frente à norma IEEE em relação aos níveis de distorção harmônica de tensão no PAC... / This work, aims to the study of the accountability problem focused on single-phase circuits with low voltage characteristics (low level of short circuit). In this scenario, the advancement of electronic loads and switchin devices have promoted and environment in which voltages and currents present high harmonic content, reducing the electrical power quality. In this context, the objective of this work is to study the behavior of linear and nonlinear loads and draw conclusions on accountability in electrical grids, i.e., responsibility in the harmonic content generation. For this purpose, it was applied the Conservative Power Theory (CPT) which is a mathematical tool for electrical circuits analysis on both sinusoidal and nonsinusoidal conditions. Furthermore, the CPT allows the application of a Accontability Methodology that takes into account information of the line impedance (equivalent Thévenin viewed by point of common coupling) and the equivalent parameters of the load. These two considerations represent a differential in relation to the studied methodologies. So, an electrical circuit containing linear and non-linear loads was proposed, and the Accountability Methodology was studied and discussed, seeking answers about the power portions that should be accontable to the harmonic loads. The load characterization and the impedance estimation presented satisfactory results. Then, the Accontability Methodology proposes that the fundamental active power should be accontable to the loads, since it represents the power portion that really flows the power source to the load. In addition, the work showed the fragility of PRODIST in relation to the IEEE standard concerning the harmonic voltage distortion established limits at the point of common coupling

The thesis is concerned with the estimation of the sampled impulse-response (SIR), of a time-varying HF channel, where the estimators are used in the receiver of a 4800 bits/s, quaternary phase shift keyed (QPSK) system, operating at 2400 bauds with an 1800 Hz carrier. T= FIF modems employing maximum-likelihood detectors at the receiver require accurate knowledge of the SIR of the channel. With this objective in view, the thesis considers a number of channel estimation techniques, using an idealised model of the data transmission system. The thesis briefly describes the ionospheric propagation medium and the factors affecting the data transmission over BF radio. It then presents an equivalent baseband model of the I-IF channel, that has three separate Rayleigh fading paths (sky waves), with a 2Hz frequency spread and transmission delays of 0,1.1 and 3 milliseconds relative to the first sky wave. Estimation techniques studied are, the Gradient estimator, the Recursive leastsquares (RLS) Kalman estimator, the Adaptive channel estimators, the Efficient channel estimator ( that takes into account prior knowledge of the number of fading paths in the channel ), and the Fast Transversal Filter (F-FF), estimator (which is a simplified form of the Kalman estimator). Several new algorithms based on the above mentioned estimation techniques are also proposed. Results of the computer simulation tests on the performance of the estimators, over a typical worst channel, are then presented. The estimators are reasonably optimized to achieve the minimum mean-square estimation error and adequate allowance has been made for stabilization before the commencement of actual measurements. The results, therefore, represent the steady-state performance of the estimators. The most significant result, obtained in this study, is the performance of the Adaptive estimator. When the characteristics of the channel are known, the Efficient estimators have the best performance and the Gradient estimators the poorest. Kalman estimators are the most complex and Gradient estimators are the simplest. Kalman estimators have a performance rather similar to that of Gradient estimators. In terms of both performance and complexity, the Adaptive estimator lies between the Kalman and Efficient estimators. FTF estimators are known to exhibit numerical instability, for which an effective stabilization technique is proposed. Simulation tests have shown that the mean squared estimation error is an adequate measurement for comparison of the performance of the estimators.

This thesis presents the work performed by the author on the application of resonantmode techniques to commercially-orientated off-line converters. An extensive review of resonant-mode topologies leads to the development of a method of categorisation of these topologies which allows a greater comprehension of their properties. The categories of converter thus obtained are the conventional resonant converter, the quasi-resonant converter, and the gap-resonant converter. The gap-resonant converter is selected for further investigation. An analysis reveals the limited load and input voltage capabilities of this converter, and hence leads to the introduction of a pre-regulating converter to improve reliability and commercial viability. High-frequency techniques are explored and reported, and new techniques are developed in several areas in order to extend the concept of the gap-resonant converter to a realworld practical design. Subjects explored include the high speed driving of power MOSFETs, MOSFET and diode switching losses, high frequency magnetic materials and core losses, and skin and proximity effects. The techniques developed are used in the design of a 30OW, off-line converter with an input voltage range of 165V to 380V after rectification, and a ten-to-one output load range.

M.Ing. / Electromagnetic Compatibility (EMC) of electronic equipment is currently an important design parameter. Layout play a significant role in the EMC of power electronic converters. This thesis describes an investigation undertaken into the electromagnetic effects of converter layout. Typical detrimental effects identified during experimental work are presented. Possible causes for these effects are discussed. The experimental work is based on a systematic approach, which starts with a basic single switch chopper and ends in a split supply half-bridge converter. Interconnection modelling and SPICE simulations of layout affects are investigated next. The focus falls on analytical equations for extraction and simplified simulation circuits to make the process generally accessible. Typical resonant frequencies present in some of the experimental circuits are investigated with the help of analytically extracted parameters. The possibility of minimizing detrimental layout effects through impedance matching of interconnections and their terminations, is investigated next, since the previous section quantified layout parameters. Distributed vs. lumped element modelling of interconnections, and the boudary in between, are discussed. Simulation and experimental results are presented. Since maximum fuctionality and power, and minimum cost, per volume drives product development, all elements of a circuit should be investigated for the possibility of realizing secondary or even tertiary functions contributing to normal circuit operation. This is the focus of the last part of this thesis. Employing interconnections as low-pass or surge filters are investigated. Several waveforms are used to test experimental interconnection structures. Lumped and distributed modelling of these strucutres are discussed. The thesis concludes with a theoretical investigation into the possibility of dissipation of surge-energy instead of reflection utilizing interconnection-structures. One of these structures utilizes the skin- and proximity effect to realize low-pass behaviour.

M.Ing. / The focus of the project is on the design of a variable output current source applied in the testing of circuit breakers. The possibility of the use of high-frequency, switch mode converters for the application, will be investigated. The expectation is the improvement of the system currently in use, with the help of a power electronic converter. For the application, a 1 to 200A adjustable current source must be developed, which will be powered from the 220V, 50Hz network. A number of possible solutions to the problem will be investigated. One of the challenges of the project is that the output of the converter must be a current and not a voltage, which is normally the case. Based on mathematical calculations and practical results, the best possible solution to the problem is obtained. An optimum system is presented, which meets the desired specifications.

M.Ing. / Low profile power electronics components are currently in great demand. The rapid advances in semiconductor and micro-electronics technology during the last ten years have played a major role in the creation of this demand. These advances are in turn driven by the need for compact design in computing, communication, consumer electronic goods and control systems with direct consequences in power supply design and manufacture. The study covered by this thesis involves the design, manufacture and thermal analysis of a planar inductor, which is a typical planar power electronics component. First, a throughout literature survey of planar magnetics revealed that satisfactory experimental procedures for the thermal analysis of passive power electronic components under operating conditions representative of modern applications are seldomly applied. Secondly, a computer based field-solver program and analytical methods are used to design and analyse a planar inductor. The applicability of different methods for determination of low power loss in passive components is discussed next. Finally, an experimental method suitable for low power loss determination is proposed and investigated. This method can be used in the analysis of inductors or capacitors of different sizes. It has a wide spectrum of application due to the advantages of frequency independence and different possible power levels.

On-device audio recognition, in particular keyword spotting, will be instrumental to realizing the promise of pervasive intelligence. On-device operation demands ultra-low power and compact area. The state of the art in fully-integrated keyword spotting chips reveals that the power and area bottleneck is not the backend keyword spotting classifier, but rather the frontend audio feature extractor, motivating research into frontend audio feature extraction that is both power- and area-efficient. After, first, introducing the topic of ultra-low power audio feature extraction using time-mode analog signal processing circuits, we, second, present an analog audio feature extractor chip that achieves the lowest power/feature and area/feature, as compared, respectively, to the most area-efficient and power-efficient published analog audio feature extractor chips. Despite the chip's state-of-the-art efficiency, competitive keyword spotting accuracy is maintained when interfacing the chip with a standard, small-footprint, software backend neural network. The chip's efficiency is due to a pair of novel circuit techniques we developed. The techniques are based on time-mode analog signal processing. This is a paradigm favored by technology scaling, in which analog information is encoded in the timing of digital edges, enabling digital gates to perform analog signal processing. Third, we present a theory-based analysis of one of the two circuit techniques. Fourth, we present theory- and simulation-based progress towards what would be a novel type of analog filtering, ``Time-Mode Analog Filter." Such a filter would use only the horizontal time axis to represent and process continuous-valued information, and would be built out of nothing more than digital gates. Fifth, and finally, we present a simulation-based study that finds that in state-of-the-art analog audio feature extractor chips, the power consumption of the critical block, the analog filterbank, can be reduced by one-and-a-half orders of magnitude, while degrading downstream keyword spotting accuracy by only a couple percent, paving the way towards more rigorous system-level design of audio recognition systems.