Grades oportunistas são ambientes distribuídos que permitem o aproveitamento do poder de processamento ocioso de recursos computacionais dispersos geograficamente em diferentes domínios administrativos. São características desses ambientes a alta heterogeneidade e a variação na disponibilidade dos seus recursos. Nesse contexto, o paradigma de agentes móveis surge como uma alternativa promissora para superar os desafios impostos na construção de grades oportunistas. Esses agentes podem ser utilizados na construção de mecanismos que permitam a progressão de execução das aplicações mesmo na presença de falhas. Esses mecanismos podem ser utilizados isoladamente, ou em conjunto, de forma a se adequar a diferentes cenários de disponibilidade de recursos. Neste trabalho, descrevemos a arquitetura do middleware MAG (Mobile Agents for Grid Computing Environment) e o que ele pode fazer em ambientes de grades oportunistas. Utilizamos esse middleware como base para a implementação de um mecanismo de tolerância a falhas baseado em replicação e salvaguarda periódica de tarefas. Por fim, analisamos os resultados obtidos através de experimentos e simulações. / Opportunistic grids are distributed environments built to leverage the computacional power of idle resources geographically spread across different administrative domains. These environments comprise many charateristics such as high level heterogeneity and variation on resource availability. The mobile agent paradigm arises as a promising alternative to overcome the construction challenges of opportunistic grids. These agents can be used to implement mechanisms that enable the progress on the execution of applications even in the presence of failures. These mechanisms can be combined in a flexible manner to meet different scenarios of resource availability. In this work, we describe the architecture of the MAG middleware (Mobile Agents for Grid Computing Environment) and what it can do in an opportunistic grid environment. We use this middleware as a foundation for the development of a fault tolerance mechanism based on task replication and checkpointing. Finally, we analize experimental and simulation results.

Advancing semiconductor technology is boosting the core count on a single chip to achieve continuously increasing performance, posing a growing demand for scalable, efficient and reliable on-chip interconnection. However this advance also makes the electronics increasingly vulnerable to faults. Inter-core connection is increasingly provided by Networks-on-Chip (NoCs), typically using conventional synchronous designs. Scaling makes it increasingly hard to avoid problems with clock distribution and in many chips a single, synchronous domain is inappropriate, anyway. In place of the well-studied synchronous NoCs, event-driven asynchronous NoCs have emerged as a promising replacement. Asynchronous NoCs have many promising advantages over synchronous ones; however, their fault-tolerance has rarely been studied. Implemented in a Quasi-Delay-Insensitive (QDI) fashion, asynchronous NoCs can achieve high timing-robustness but show complicated failure scenarios in the presence of faults and behave differently from synchronous ones, posing a challenge to asynchronous circuit advocates. This research studies the impact of different faults on QDI NoC fabrics and presents thorough and systematic fault-tolerant solutions at the circuit level, providing a holistic, efficient and resilient interconnection solution for QDI NoCs. The contributions of this research include: 1) a thorough analysis of fault impact on QDI NoCs; 2) a Delay-Insensitive Redundant Check (DIRC) coding scheme protecting QDI links from transient faults; 3) a novel time-out technique detecting the fault-caused physical-layer deadlock in a QDI NoC (the adaptability of a QDI circuit to timing variation makes it vulnerable to this kind of deadlock); 4) a fine-grained recovery technique utilising a Spatial Division Multiplexing (SDM) implementation to recover the deadlocked network from a link fault. Both unprotected and protected QDI NoCs are implemented, along with a fault simulation environment, to provide a detailed performance and fault-tolerance evaluation of these techniques. The improvements to the NoC operation, together with the costs in circuit overhead and throughput are enumerated using a typical example of QDI interconnection.

Les systèmes électroniques sont de plus en plus présents dans les sociétés modernes, on peut les retrouver sous des formes très variées, très simple comme le réveil au chevet du lit ou très complexe comme un satellite de télécommunication en orbite. De nos jours, la majorité de ces inventions reposent en partie sur des "systèmes sur puces" afin de parvenir à accomplir leurs fonction principale, à savoir nous simplifier notre quotidien.Toutefois, à cause de leur nature physique, ces systèmes peuvent subir des dysfonctionnements dûs aux environnements dans lesquels ils évoluent. Des phénomènes naturels peuvent provoquer des aléas susceptibles d'avoir des conséquences graves sur la sûreté de fonctionnement du système.Cette thèse étudie la fiabilité d'une classe spécifique de systèmes sur puce capables de se reconfigurer partiellement de manière dynamique. Nous explorons la possibilité d'utiliser leur capacité de reconfiguration dynamique partielle (RDP) pour durcir les applications sur FPGAs. Nous avons proposé l'utilisation des approches de sauvegarde et de restauration de contexte pour la tolérance contre les fautes transitoire. La RDP est utilisée pour la gestion de contexte des tâches matérielles de l'application reconfigurable, le recours à la RDP permet de réduire les modifications à apporter au système initial et la complexité du système résultant. Après identification des limitations de l'approche "Backward Error Recovery" sur les plateformes FPGAs à base de mémoire SRAM, nous proposons un nouveau algorithme de placement des ressources sur FPGA afin de minimiser les temps d'accès des opérations de sauvegarde et de restauration d'une tâche matérielle. L'évaluation de la fiabilité de notre approche est réalisée à travers une campagne d'injection de faute sur une plateforme de démonstration basée sur un FPGA Virtex-5 qui intègre le contrôleur de fiabilité et une application de chiffrement de données. / Electronic systems are a growing need in modern societies, they can be found in a variety of forms, simple as an Alarm Clock at the bedside or very complex as a telecommunications satellite into orbit. Today, the majority of these inventions are based mainly on "systems on chips", in order to achieve their primary function: simplify our daily lives.However, because of their physical nature, these systems can suffer from malfunctions due to the environments in which they operate. Natural phenomena can cause hazards which may have serious consequences on system dependability.This thesis focuses on a specific class of systems on chip which are able to reconfigure dynamically and partially and their reliability. We explore the possibility of using their partial dynamic reconfiguration capability (PDR) for hardening applications on FPGAs. We have proposed the use of checkpoint approaches and context restoration for tolerance against transient faults. PDR is used for managing the context of hardware tasks present on the application. the use of RDP reduces changes to the original system and therefore the complexity of the resulting system. After identifying the limitations of the "Backward Error Recovery" approach into SRAM-based FPGAs platforms, we propose a new resource placement algorithm on FPGA to minimize the access time needed by check-pointing and rolling back operations of hardware tasks. The evaluation of the overall reliability of our approach is achieved through fault injection campaign on demonstration platform running on a Virtex-5 that integrates our reliability controller and hosts a data encryption application.

Intelligent Transportation Systems (ITS) are gaining momentum among researchers. ITS encompasses several technologies, including wireless communications, sensor networks, data and voice communication, real-time driving assistant systems, etc. These states of the art technologies are expected to pave the way for a plethora of vehicular network applications. In fact, recently we have witnessed a growing interest in Vehicular Networks from both the research community and industry. Several potential applications of Vehicular Networks are envisioned such as road safety and security, traffic monitoring and driving comfort, just to mention a few. It is critical that the existence of convenience or driving comfort services do not negatively affect the performance of safety services. In essence, the dissemination of safety services or the discovery of convenience applications requires the communication among service providers and service requesters through constrained bandwidth resources. Therefore, service discovery techniques for vehicular networks must efficiently use the available common resources. In this thesis, we focus on the design of bandwidth-efficient and scalable service discovery protocols for Vehicular Networks. Three types of service discovery architectures are introduced: infrastructure-less, infrastructure-based, and hybrid architectures. Our proposed algorithms are network layer based where service discovery messages are integrated into the routing messages for a lightweight discovery. Moreover, our protocols use the channel diversity for efficient service discovery. We describe our algorithms and discuss their implementation. Finally, we present the main results of the extensive set of simulation experiments that have been used in order to evaluate their performance.

Dans cette thèse, nous nous sommes intéressés à l'étude des modèles comportementaux en mode dégradé des machines pentaphasées à commutation de flux (MCF pentaphasée). Tout d'abord, une comparaison des performances électromagnétiques de cette machine à une machine triphasée équivalente est tout d'abord effectuée. Ces performances sont calculées par la méthode des Eléments Finis (EF 2D) et validées expérimentalement. Les résultats ont montré l'apport de la machine pentaphasée avec un couple massique plus élevé, une ondulation de couple plus faible, un courant de court-circuit plus faible et sa capacité à tolérer des défauts de phases. L'étude de la tolérance aux ouvertures de phases est alors élaborée pour cette MCF pentaphasée. Le comportement de la machine en cas d'ouvertures de phases (du point de vue du couple moyen, de l'ondulation de couple, des pertes Joule et du courant dans le neutre) est présenté. Ensuite, des méthodes de reconfiguration en vue d'améliorer le fonctionnement sont proposées dont une reconfiguration minimale permettant de se retrouver avec une alimentation équivalente à celle d'une machine tétraphasée ou triphasée, un calcul analytique des courants optimaux permettant d'annuler à la fois le courant du neutre et l'ondulation du couple tout en assurant le couple moyen, et finalement une reconfiguration assurée par un algorithme génétique d'optimisation qui est un algorithme non-déterministe multi-objectifs et multi-contraintes. Diverses combinaisons des différents objectifs et contraintes sont, dans ce cadre, effectuées et les courants optimaux sont injectés dans le modèle EF 2D de la machine pour vérifier si les performances ont été améliorées. Le modèle analytique du couple pris en compte dans l'algorithme d'optimisation est alors révisé pour prendre en compte l'influence du mode dégradé. Les différentes solutions du front de Pareto sont analysées et les performances électromagnétiques sont bien améliorées. Cela est vérifié par les calculs EF 2D et suivi d'une validation expérimentale. L'influence des défauts sur les forces magnétiques radiales est également analysée. Dans une seconde partie, l'étude de la tolérance de la machine pentaphasée à commutation de flux aux défauts de courts-circuits est effectuée. Les premières étapes d'isolation des défauts de courts-circuits sont proposées. Par la suite, les courants de courts-circuits, prenant en compte l'effet reluctant de la machine, sont calculés analytiquement et leurs effets sur les performances de la machine sont analysés. Les reconfigurations sont aussi calculées par l'algorithme génétique d'optimisation et les nouvelles références des courants permettent d'améliorer le fonctionnement en mode dégradé. Tous les résultats sont validés par la méthode des EF 2D et expérimentalement. En conclusion, des comparaisons entre la tolérance aux défauts d'ouvertures et de courts-circuits de la machine pentaphasée à commutation de flux sont effectuées et ont permis de conclure quant au fonctionnement de cette machine en modes sain et dégradé avec et sans correction. Les résultats analytiques, numériques et expérimentaux ont montré la bonne efficacité de la commande proposée pour l'amélioration de la tolérance aux défauts d'ouvertures et courts-circuits de phases. / In this thesis, we are interested in the study of a five-phase flux switching permanent magnet machine (five-phase FSPM machine) behavior in healthy and faulty mode. First, a comparison of electromagnetic performances between this machine and an equivalent three-phase machine is carried out. These performances are calculated by a Finite Element (FE 2D) model and validated by experiments. Results showed the five-phase machine contribution with a higher torque density, lower torque ripples, lower short-circuit current and ability to tolerate phases faults. The study of open-circuit tolerance is then developed for this five-phase FSPM. The behavior of the machine (the average torque, torque ripples, copper losses and the current in the neutral) in the case of open-circuit on a single and two adjacent and non-adjacent phases is presented. Then reconfiguration methods to improve the operation are proposed including a minimum reconfiguration allowing to end up with a feeding equivalent to that of a three-phase or a four-phase machine, an analytical calculation of optimal currents to cancel both the neutral current and torque ripples while ensuring the average torque, and finally a reconfiguration performed by a genetic optimization algorithm which is a non-deterministic algorithm multi-objective functions and multi-constraints. In this context, various combinations of different objectives and constraints are proposed and optimal currents are injected into the 2D FE model of the machine to see if performances have been improved. The analytical model of the torque used in the optimization algorithm is then revised to take into account the influence of the degraded mode. Different solutions of Pareto front are analyzed and electromagnetic performances are improved. This is verified by FE 2D calculations and followed by experimental validation. Faults impact on the radial magnetic forces is also analyzed. In the second part of this work, the study of the five-phase FSPM machine tolerance to short-circuit faults is performed. First steps of the faults isolation are proposed. Thereafter, short-circuit currents, taking into account the reluctance machine impact, are calculated analytically and their effects on machine performances are analyzed. Reconfigurations are also calculated by the genetic algorithm optimization and new references currents improved the degraded mode operation. All results are validated by the FE 2D calculation and experimentally. In conclusion, comparisons between fault-tolerance to phases openings and short-circuits of the five-phase FSPM machine are performed. Results led to conclude regarding the operation of this machine in healthy and degraded modes with and without correction. Analytical, numerical and experimental results showed good efficiency of the proposed control to improve fault-tolerance to phases openings and short-circuits.

De nos jours, les systèmes distribués doivent répondre de plus en plus à de nouvelles exigences de qualité de service et à l’émergence de nouvelles applications comme le calcul sur la grille ; ce qui généralement se traduit par des impératifs de dynamicité et de mobilité. Si des solutions satisfaisantes existent pour des environnements distribués statiques, elles sont inadaptées dans le cas où le système devient dynamique (mobilité, évolution, modification de composants). En effet, la conception d’algorithmes distribués est traditionnellement fondée sur l’hypothèse d’un réseau dont la topologie est statique. Notre objectif dans cette thèse est de définir et d’étudier un modèle à base d’agents mobiles pour l’implémentation et l’exécution d’algorithmes distribués codés par des calculs locaux.Ce modèle doit tenir en compte des pannes qui peuvent altérer le fonctionnement du système distribué. Il doit aussi améliorer les performances vis-à-vis des modèles classiques (à envoi de messages) / Today, distributed systems must satisfy increasinglynew requirements for quality of service and the emergence ofnew applications such as Grid Computing, whichgenerally results in requirements of dynamicity andmobility. If satisfactory solutions exist forstatic distributed environments, they are inadequate in the casewhere the system becomes dynamic (mobility, evolution,components change). Indeed, the design of distributed algorithms istraditionally based on the assumption of a network whosetopology is static. Our goal, in this thesis, is to defineand study a model based on mobile agents to implementand execute distributed algorithms encoded by local computations.This model must take into account failures that can alter thethe distributed system operation. It should also improveperformance vis-à-vis the classical models (message passing systems)

Esta dissertação de mestrado tem como objetivo avaliar a integração de políticas de tolerância a falhas em uma arquitetura de Web Services com múltiplos módulos. A arquitetura utilizada é denominada WSARCH, e foi desenvolvida para o estudo das relações e interoperabilidade entre serviçcos. Os mecanismos de tolerência a falhas foram integrados aos módulos da arquitetura, testados, comparados e avaliados. A avaliação de desempenho mostrou que os mecanismos de tolerância a falhas introduzidos foram eficientes e apresentaram resultados adequados. As técnicas de reputação utilizadas na seleção de serviço atuaram satisfatoriamente e foram consideradas um importante avanço nos mecanismos da arquitetura / This master\'s thesis aims to evaluate the integration of fault tolerance mechanisms in a Web Services architecture with multiple modules. The architecture used is named WSARCH and was developed for the study of interactions and interoperability of services. WSARCH is an architecture conceived to receive tests and experiments involving concepts of Web Services. The fault tolerance tools were integrated in the architecture, tested, evaluated and comparated. The performance evaluation showed that the fault tolerance mechanisms introduced were ecient and presented appropriate results. The reputation techniques utilized in service selection operated successfully and were considered an important advance in the mechanisms of the architecture

Wireless Sensor Networks (WSN) are distributed sensing network systems composed of tiny networked devices. These systems are employed to develop applications for sensing and acting on the environment. Each network device, or node, is equipped with sensors and sometimes actuators as well. WSNs typically have limited power, processing, and storage capability, and are also subject to faults, especially when deployed in harsh environments. Given WSNs limitations, application developers often design fault-tolerance mechanisms. Although developers implement some fault-tolerance mechanisms in hardware, most are implemented in software. Indeed, WSN application development mostly occurs at a low level, close to the operating system, which forces developers to focus away from application logic and dive into WSNs technical background. Some have proposed high-level programming solutions, such as macroprogramming languages and frameworks; however, few deal with fault-tolerance. This dissertation aims to incorporate fault-tolerance features into Srijan, an open-source WSN macroprogramming framework based on a mixed declarative-imperative language called Abstract Task Graph (ATaG). We augment Srijans framework to support code generation for dealing with devices that crash or report meaningless values. We present our feature implementation here, along with an evaluation of the tool, demonstrating that it is possible to provide a macroprogramming framework with appropriate support for developing fault-tolerant WSN applications. / Redes de Sensores Sem Fio (RSSF) são sistemas distribuídos em rede para sensoreamento, compostos de pequenos dispositivos conectados entre si. Esses sistemas são utilizados para construir aplicações que medem e atuam no meio físico. Cada dispositivo da rede, chamado de nó, é equipado com sensores, e algumas vezes, atuadores. Os nós também comumente possuem limitações em termos de suprimento de energia e capacidade de armazenamento e processamento. Em adição à essas limitações, redes de sensores sem fio também estão sujeitas à diversos tipos de falhas, especialmente quando são implantadas em ambientes de condições naturais extremas, como florestas e plantações. Por essas razões, desenvolvedores de aplicações para redes de sensores sem fio necessitam utilizar mecanismos de tolerância a falhas. Alguns dos mecanismos de tolerância a falhas são implementados em hardware, porém são mais comumente deixados para implementação em software. Além disso, a maior parte do desenvolvimento de aplicações para RSSF é feita em baixo nível de abstração, perto do sistema operacional. Desse modo, além de terem que concentrar-se na lógica da aplicação em baixo nível, os desenvolvedores ainda têm que implementar os mecanismos de tolerância a falhas junto à aplicação, pela falta de bibliotecas ou componentes genéricos para esse fim. Técnicas de programação em alto nível para RSSF já foram propostas na forma de linguagens e arcabouços de macroprogramação. No entanto, uma minoria lida com aspectos de tolerância a falhas. O objetivo desse trabalho é incorporar funcionalidades para tolerância a falhas ao Srijan, um arcabouço de macroprogramação para redes de sensores sem fio. Srijan possui código aberto e é baseado em uma linguagem mista declarativa-imperativa chamada Abstract Task Graph (ATaG). Evoluímos o arcabouço para dar suporte à geração automática de código lidando com quedas de nós da rede e falhas que resultam em dados incorretos de sensores. Nesta dissertação, apresentamos a nossa implementação de tais funcionalidades, juntamente com a avaliação conduzida sobre a ferramenta. Mostramos que é possível prover um arcabouço de macroprogramação com suporte apropriado ao desenvolvimento de aplicações para RSSF que necessitam tolerância a falhas.

Os efeitos de radiação têm sido um dos problemas mais sérios em aplicações militares e espaciais. Mas eles também são uma preocupação crescente em tecnologias modernas, mesmo para aplicações comerciais no nível do solo. A proteção dos circuitos integrados contra os efeitos da radiação podem ser obtidos através do uso de processos de fabricação aprimorados e de estratégias em diferentes estágios do projeto do circuito. A técnica de TMR é bem conhecida e amplamente empregada para mascarar falhas únicas sem detectálas. No entanto, o projeto de circuitos TMR não é automatizado por ferramentas EDA comerciais e até mesmo eles podem remover parcial ou totalmente a lógica redundante. Por outro lado, existem várias ferramentas que podem ser usadas para implementar a técnica de TMR em circuitos integrados, embora a maioria delas sejam ferramentas comerciais licenciadas, convenientes apenas para dispositivos específicos, ou com uso restrito por causa do regime ITAR. O presente trabalho pretende superar esses incovenientes, para isso uma metodologia é proposta para automatizar o projeto de circuitos TMR utilizando um fluxo de projeto comercial. A abordagem proposta utiliza um netlist estruturado para implementar automaticamente os circuitos TMR em diferentes níveis de granularidade de redundância para projetos baseados em células e FPGA. A otimização do circuito TMR resultante também é aplicada com base na abordagem do dimensionamento de portas lógicas. Além disso, a verificação do circuito TMR implementado é baseada na verificação de equivalência e garante sua funcionalidade correta e sua capacidade de tolerancia a falhas simples. Experimentos com um circuito derivado de HLS e uma descrição ofuscada do soft-core ARM Cortex-M0 foram realizados para mostrar o uso e as vantagens do fluxo de projeto proposto. Diversas questões relacionadas à remoção da lógica redundante implementada foram encontradas, bem como o impacto no incremento de área causado pelos votadores de maioria. Além disso, a confiabilidade de diferentes implementações de TMR do soft core ARM sintetizado em FPGA foi avaliada usando campanhas de injeção de falhas emuladas. Como resultado, foi reforçado o nível de alta confiabilidade da implemntação com mais fina granularidade, mesmo na presença de até 10 falhas acumuladas, e a menor capacidade de mitigação correspondente à replicação de flip-flops apenas. / Radiation effects have been one of the most serious issues in military and space applications. But they are also an increasing concern in modern technologies, even for commercial applications at the ground level. Protection or hardening of integrated circuits against radiation effects can be obtained through the use of enhanced fabrication processes and strategies at different stages of the circuit design. The triple modular redundancy (TMR) technique is a widely and well-known technique employed to mask single faults without detecting them. However, the design of TMR circuits is not automated by commercial electronic design automation (EDA) tools and even they can remove partially or totally the redundant logic. On the other hand, there are several tools that can be used to implement the TMR technique in integrated circuits, although most of them are licensed commercial tools, convenient only for specific devices, or with restricted use because of the International Traffic in Arms Regulations (ITAR) regimen. The present work intends to overcome these issues so a methodology is proposed to automate the design of TMR circuits using a commercial design flow. The proposed approach uses a structured netlist to implement automatically TMR circuits at different granularity levels of redundancy for cell-based and field-programmable gate array (FPGA) designs. Optimization of the resulting TMR circuit is also applied based on the gate sizing approach. Moreover, verification of the implemented TMR circuit is based on equivalence checking, and guarantee its correct functionality and its fault-tolerant capability against soft errors. Experiments with an high-level synthesis (HLS)-derived circuit and an obfuscated description of the ARM Cortex-M0 soft-core are performed to show the use and the advantages of the proposed design flow. Several issues related to the removal of the implemented redundant logic were found as well as the impact in the increment of area caused by the majority voters. Furthermore, the reliability of different TMR implementations of the ARM soft-core synthesized in FPGA was evaluated using emulated-simulation fault injection campaigns. As a result, it was reinforced the high-reliability level of the finest granularity implementation even in the presence of up to 10 accumulated faults and the poorest mitigation capacity corresponding to the replication of flip-flops solely.

Le travail de cette thèse s’inscrit dans une thématique qui concerne le dimensionnement optimal et la gestion d’énergie résiliente aux défauts d’un système multi-sources (hybride) pour l’alimentation d’un véhicule électrique. Dans notre cas, le système de stockage est composé d’une pile à combustible comme source principale et une source secondaire à base d’une batterie Li-ion. L’étude réalisée sur le dimensionnement montre l’intérêt de l’hybridation par rapport à un système mono-source batterie seule ou bien pile à combustible seule. L’intérêt de cette hybridation en termes de masse, de volume et de coût devient de plus en plus important en augmentant l’autonomie du véhicule. Après avoir dimensionné la source hybride pour une autonomie de 700 km, on s’est intéressé à l’influence de la technologie de la batterie et les méthodes de gestion sur les performances de la source (le volume, la masse, le cout, les contraintes électriques appliquées sur les composants et la consommation d’hydrogène du système PàC/Batterie). La partie dimensionnement est suivie par le développement d’une stratégie de gestion d’énergie originale basée sur la prise en compte de l’état de charge de la batterie (SOC) pour adapter les limites de fonctionnement de la pile à combustible. Les résultats obtenus avec cette méthode sont comparés avec deux autres stratégies de gestion d’énergie en ligne à savoir, la méthode de découpage fréquentiel et l’utilisation d’un superviseur floue. La stratégie développée a donné des bons résultats expérimentaux en termes de contraintes vues par les cellules et de consommation d’hydrogène. Malgré un bon dimensionnement de la source embarquée et une bonne optimisation de la méthode de gestion d’énergie, le système n’est pas à l’abri du défaut et peut être le siège de plusieurs défauts qui peuvent apparaitre au niveau de capteurs de tension et de courant. Afin d’assurer la continuité de service du système hybride en présence de ces défauts, une stratégie de commande tolérante aux fautes a été développée afin de garantir la stabilité de système hybride PàC/Batterie et assurer des performances acceptables en mode dégradé. / The work of this thesis is part of a theme that concerns the optimal sizing and energy management resilient to the faults of a multi-source system (hybrid) for the power supply of an electric vehicle. In our case, the storage system consists of a fuel cell as the main source and a secondary source based on a Li-ion battery. The study carried out on the sizing shows the interest of the hybridization compared to a mono-source single battery or fuel cell only system. The interest of this hybridization in terms of weight, volume and cost becomes more and more important by increasing the autonomy of the vehicle. After scaling the hybrid source for a 700 km drive range, we investigated the influence of battery technology and management methods on the performance of the source (volume, mass, cost, electrical stress applied to the components and the hydrogen consumption of the Fuel Cell / Battery system).The sizing part is followed by the development of an original energy management strategy based on the state of charge of the battery (SOC) to adapt the operating limits of the fuel cell. The results obtained with this method are compared with two other online energy management strategies namely, the frequency division method and the use of a fuzzy supervisor. The strategy developed gave good experimental results in terms of constraints seen by cells and hydrogen consumption. Despite a good sizing of the on-board source and a good optimization of the energy management method, the system is not immune from the fault and can be the seat of several faults that can appear at voltage sensors. and current. In order to ensure the service continuity of the hybrid system in the presence of these faults, a fault-tolerant control strategy has been developed in order to guarantee the stability of the hybrid Fuel Cell/ Battery system and to ensure acceptable performance in degraded mode.