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Background: The Covid-19 pandemic has affected the global economy, as governments imposed restrictions on mobility and social distancing. As a consequence many businesses shifted their daily activities to remote channels. The urgent shift meant a lack in organizational and workforce readiness to integrate the change in daily routines. Hence, as the majority of organizations adapt remote practices, it is critical to address the fundamental and contextual consequences within the current framework.  Purpose: The aim of this study is to investigate the shift in organizational hierarchy as a consequence of the implementation of remote work in regards to the Covid-19 pandemic.  Methodology: A quantitative research design was applied, where primary data was collected through surveys. The sample size consisted of 47 participants that were currently employed in Sweden and had experienced a shift to remote work during the pandemic (2020-2022). Moreover, the participants have been employed during the period 2017-2022, as the intention was to compare the perceptions before and after the pandemic.  Findings: The findings revealed that no significant change in hierarchical structure had occurred due to the shift to remote work. Empirical evidence proposed a significant decrease in response times between different departments; nonetheless, the following is not evident enough to support a shift in hierarchical structure. There was an evident shift in one out of six leadership styles, as adaptation of task-oriented leadership decreased. The shift was further explained by a task-oriented approach exemplifying autocratic characteristics, that in turn malfunctioned in times of urgency. Finally, there has been a decrease in satisfaction concerning work environment and social interactions with colleagues. Overall, the study lacked empirical evidence that indicated a prominent shift in hierarchical structures or leadership style.  Implications for future research: The current study found implications on diminishing satisfaction related to the work environment perceptions. Thus, suggestions for future research include a focus on investigating the causations of the aforementioned issues. The underlying reasons for the shift from task-oriented leadership could be further explored, as previous research argues for its benefits in the context of leading virtual teams. Finally, there is development potential in exploring the shift of perceptions from different employment configurations, which might be influential in the context of hierarchical reflections.

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This dissertation addresses the problem of making system level design (SLD) methodology based on SystemC more useful to the complex embedded system design community by presenting a number of ingredients currently absent in the existing SLD methodologies and frameworks. The complexity of embedded systems have been increasing at a rapid rate due to proliferation of desired functionality of such systems (e.g., cell phones, game consoles, hand-held devices, etc., are providing more features every few months), and the device technology still riding the curve predicted by Moore's law. Design methodology is shifting slowly towards system level design (also called electronic system level (ESL)). A number of SLD languages and supporting frameworks are being proposed. SystemC is positioned as being one of the dominant SLD languages. The various design automation tool vendors are proposing frameworks for supporting SystemC-based design methodologies. We believe that compared to the necessity and potential of ESL, the success of the frameworks have been limited due to lack of support for a number of facilities and features in the languages and tool environments. This dissertation proposes, formulates, and provides proof of concept demonstrations of a number of ingredients that we have identified as essential for efficient and productive use of SystemC-based tools and techniques. These are heterogeneity in the form of multiple models of computation, behavioral hierarchy in addition to structural hierarchy, model-driven validation for SystemC designs and a service-oriented tool integration environment. In particular, we define syntactic extensions to the SystemC language, semantic modifications, and simulation algorithms, precise semantics for model based validation etc. For each of these we provide reference implementation for further experimentation on the utility of these extensions. / Ph. D.

This research investigated methods to determine appropriate security protocols for specific wireless network applications. The specific problem being addressed was that there are tradeoffs between security, performance, and efficiency among current and proposed security protocols. Performance and efficiency issues are particularly important in wireless networks which tend to have constrained network capacity and connect to resource-limited nodes. Existing security protocols address problems such as authentication, availability, confidentiality, integrity, and non-repudiation. However, these protocols use resources and limit the efficient use of node resources. Thus, the overall objective of this research is to improve the efficiency of security mechanisms for wireless networks. A methodology was constructed to satisfy this objective and is an important contribution of this research. The methodology can be used to define the relevant operational parameters of different wireless network applications, classify wireless networks into distinct categories, incorporate appropriate security protocols to a category, and analyze the security protocols through metrics. Three groups of operational parameters were created to classify wireless networks; these are equipment, network topology, and communication characteristics. The wireless network categories include, but are not limited to, fixed broadband wireless networks, wireless local area networks, mobile ad hoc networks, and small device sensor networks. The metrics in the methodology are used to measure end-to-end data throughput and delay, efficiency and overhead, power and energy consumption, and energy consumed per packet transferred. The main advantage of this methodology is the flexibility of how constraints are considered and suitability is analyzed. This approach can identify problems from manageable categories of networks and find or create solutions for each of them. Another advantage of this methodology is that after suitable security protocols are found or created for each category, any new wireless network application that falls into an existing category may be able to use the security protocols from that category and find that they are the most suitable. Another key contribution of this research was the implementation and evaluation of a context aware and adaptive security manager (CASM) that selects appropriate protocols in real-time. CASM was developed using the methodology as a guide. Results from a resource analysis of four encryption algorithms were utilized for the design of CASM. A feasibility study of CASM was then completed. Three different experimental scenarios were used to evaluate CASM's operation. The results and analysis of the experiments indicate that the security manager functions properly and security is provided efficiently with different user settings and environments. Three schemes were deemed the best to use for the decision module of CASM. / Ph. D.

The thesis is an investigation into the discipline of architecture. A building project serves as a tool in this investigation. The building project uses frame and skin elements to study the means of articulating a wall. Hierarchy, urban debris and scale relationships control this articulation. The design intentions are rooted in an understanding of architecture as the stage for the life of the city. / Master of Architecture

Because of their ubiquity and low cost fabrication techniques, electronic textiles (e-textiles) are an excellent platform for pervasive computing. Many e-textile applications are already available in the commercial, military, and academic domains, but most are very highly specialized and do not lend themselves easily to reuse or alteration. The purpose of this work is threefold: development of a methodology for building flexible and reusable applications that facilitates their use in the evolution of more complex systems, creation of a resource manager that realizes the methodology and enforces quality of service guarantees on tightly constrained textile resources, and construction of a simulation environment that allows for the rapid development and reconfiguration of systems to circumvent the need for the expensive physical prototyping process. This work discuss the effectiveness and appropriateness of the deployed event-driven hierarchical service model for application development. Additionally, this work explores the results of providing fault tolerance and quality of service guarantees in a textile environment that is particularly susceptible to faults. Further addressed by this work is the success of rapid prototyping and evaluation of applications in the simulation environment. / Master of Science

This thesis focuses on practical and quantitative methods for measuring effectiveness in naval ship design. An Overall Measure of Effectiveness (OMOE) model or function is an essential prerequisite for optimization and design trade-off. This effectiveness can be limited to individual ship missions or extend to missions within a task group or larger context. A method is presented that uses the Analytic Hierarchy Process combined with Multi-Attribute Value Theory to build an Overall Measure of Effectiveness and Overall Measure of Risk function to properly rank and approximately measure the relative mission effectiveness and risk of design alternatives, using trained expert opinion to replace complex analysis tools. A validation of this method is achieved through experimentation comparing ships ranked by the method with direct ranking of the ships through war gaming scenarios. The second part of this thesis presents a mathematical ship synthesis model to be used in early concept development stages of the ship design process. Tools to simplify and introduce greater accuracy are described and developed. Response Surface Models and Design of Experiments simplify and speed up the process. Finite element codes such as MAESTRO improve the accuracy of the ship synthesis models which in turn lower costs later in the design process. A case study of an Advanced Logistics Delivery Ship (ALDV) is performed to asses the use of RSM and DOE methods to minimize computation time when using high-fidelity codes early in the naval ship design process. / Master of Science

Thesis advisor: David G. Hunter / Thesis advisor: Samuel Fernández / Origen of Alexandria (ca. 185–253) produced a comprehensive theological narrative of salvation history, from protology to eschatology, based on his interpretation of Scripture. More than one “plotline” is being developed throughout Origen’s unique rendition or performance of the Christian drama of salvation history. The primary goal of this dissertation is to bring the political dimension of Origen’s theological narrative into focus. To this end, it examines the constitutive elements of political thought in Late Antiquity—community, justice, and rulership—as thematic loci within Origen’s theological narrative. By tracking Origen’s development of this political plotline, from beginning to end, this dissertation provides the first systematic treatment of what may be called Origen’s “political theology.” This dissertation also provides an original study of how the political language, models, and themes of Scripture were received into Origen’s theology (e.g., the “Kingdom” and “City” of God, as well as the Pauline “rulers, powers, and authorities”). Within this political framework, Origen discusses the following: (1) the form and method of God’s rulership, (2) the compatibility of the creation’s freedom and its subjection to God’s rulership, (3) the arrangement of creatures into a cosmic hierarchy of rulers and ruled, (4) the justice of God’s rulership, (5) Christ as the form or archetype of Justice, (6) Christ’s restoration of both ruling and obedience within the created order, and (7) the realization of a divine πολιτεία. These are the main topics considered in this study. / Thesis (PhD) — Boston College, 2024. / Submitted to: Boston College. Graduate School of Arts and Sciences. / Discipline: Theology.

Tesis por compendio / [ES] En los últimos años, la creciente necesidad de la capacidad de cómputo ha supuesto un reto que ha llevado a la industria a buscar arquitecturas alternativas a los procesadores superescalares con ejecución fuera de orden convencionales, con el objetivo de incrementar la potencia de cómputo con una mayor eficiencia energética. Las GPU, que hasta hace apenas una década se dedicaban exclusivamente a la aceleración de los gráficos en los computadores, han sido una de las arquitecturas alternativas más utilizadas durante varios años para alcanzar el mencionado objetivo. Una de las características particulares de las GPU es su gran ancho de banda para acceder a memoria principal, lo que les permite ejecutar un gran número de hilos de forma muy eficiente. Esta característica, así como su elevada potencia computacional ejecutando operaciones de coma flotante, ha originado la aparición del paradigma de computación denominado GPGPU computing, paradigma en el que las GPU realizan cómputo de propósito general. Las citadas características convierten a las GPU en dispositivos especialmente apropiados para la ejecución de aplicaciones masivamente paralelas que tradicionalmente se habían ejecutado en procesadores convencionales de altas prestaciones. El trabajo desarrollado en esta tesis persigue ayudar a mejorar las prestaciones de las GPU en la ejecución de aplicaciones GPGPU. Con este fin, como primer paso, se realiza un estudio de caracterización donde se identifican las características más importantes de estas aplicaciones desde el punto de vista de la jerarquía de memoria y su impacto en las prestaciones. Para ello, se utiliza un simulador detallado ciclo a ciclo donde se modela la arquitectura de una GPU reciente. El estudio revela que es necesario modelar de forma más detallada algunos componentes críticos de la jerarquía de memoria de las GPU para obtener resultados precisos. Los resultados obtenidos muestran que las prestaciones alcanzadas pueden variar hasta en un factor de 3× dependiendo de cómo se modelen estos componentes críticos. Por este motivo, como segundo paso antes de elaborar la propuesta de mejora, el trabajo se centra en determinar qué componentes de la jerarquía de memoria de la GPU necesitan modelarse con mayor detalle para mejorar la precisión de los resultados del simulador, y en mejorar los modelos existentes de estos componentes. Además, se realiza un estudio de validación que compara los resultados obtenidos con los modelos mejorados contra los de una GPU comercial real. Las mejoras implementadas reducen la desviación de los resultados del simulador sobre los resultados reales alrededor de un 96%. Finalmente, una vez mejorada la precisión del simulador, en esta tesis se presenta una propuesta innovadora, denominada FRC (siglas en inglés de Fetch and Replacement Cache), que mejora en gran medida la potencia computacional de la GPU, gracias a que aumenta el paralelismo en el acceso a memoria principal. La propuesta incrementa el número de accesos en paralelo a memoria principal mediante la aceleración de la gestión de las acciones de búsqueda y reemplazo relacionadas con los accesos que fallan en la cache. La propuesta FRC se basa en una pequeña estructura cache auxiliar que descongestiona el subsistema de memoria eficientemente, aumentando las prestaciones de la GPU hasta un 118% de media respecto al sistema base. Además, también reduce en 57% el consumo energético de la jerarquía de memoria. / [CA] En els últims anys, la creixent necessitat de capacitat de còmput ha suposat un repte que ha portat a la indústria a buscar arquitectures alternatives als processadors superescalars amb execució fora d'ordre convencionals, amb l'objectiu d'incrementar la potència de còmput alhora que s'aconsegueix una major eficiència energètica. Les arquitectures GPU, les quals fins fa només una dècada es dedicaven exclusivament a l'acceleració dels gràfics en els computadors, han sigut una de les alternatives més utilitzades durant alguns anys per a aconseguir l'esmentat objectiu. Una de les característiques particulars de les GPU és el seu elevat ample de banda per a accedir a memòria principal, la qual cosa permet executar un gran nombre de fils de forma molt eficient. Aquesta característica, així com la seua elevada potència computacional executant operacions de coma flotant, ha originat l'aparició del paradigma de computació anomenat GPGPU computing, paradigma on les GPU realitzen còmput de propòsit general. Les citades característiques converteixen a les GPU en dispositius especialment apropiats per a l'execució d'aplicacions massivament paral·leles que tradicionalment s'havien executat en processadors convencionals d'altes prestacions. El treball desenvolupat en aquesta tesi persegueix ajudar a millorar les prestacions de les GPU en l'execució de les aplicacions GPGPU. A aquest efecte, com a primer pas, es realitza un estudi de caracterització on s'identifiquen les característiques més importants d'aquestes aplicacions des del punt de vista de la jerarquia de memòria i el seu impacte en les prestacions. Per a això s'utilitza un simulador detallat cicle a cicle on es modela l'arquitectura d'una GPU recent. L'estudi revela que és necessari modelar de forma més detallada alguns components crítics de la jerarquia de memòria de les GPU per a obtindre resultats precisos. Els resultats obtinguts mostren que les prestacions aconseguides poden variar fins i tot en un factor de 3× depenent de com es modelen aquests components crítics. Per aquest motiu, com a segon pas abans d'elaborar la proposta de millora, el treball se centra en determinar quins components de la jerarquia de memòria de la GPU necessiten modelar-se amb major detall per a millorar la precisió dels resultats del simulador i en millorar els models existents d'aquests components. A més, es realitza un estudi de validació que compara els resultats obtinguts amb els models millorats contra els d'una GPU comercial real. Les millores implementades redueixen la desviació dels resultats del simulador sobre els resultats reals al voltant d'un 96%. Finalment, una vegada millorada la precisió del simulador, en aquesta tesi es presenta una proposta innovadora, denominada FRC (sigles en anglés de Fetch and Replacement Cache), que millora en gran manera la potència computacional de la GPU, gràcies a que augmenta el paral·lelisme en l'accés a memòria principal. La proposta incrementa el nombre d'accessos en paral·lel a memòria principal mitjançant l'acceleració de la gestió de les accions de recerca i reemplaçament relacionades amb els accessos que fallen en la cache. La proposta FRC es basa en una xicoteta estructura cache auxiliar que descongestiona el subsistema de memòria eficientment, augmentant les prestacions de la GPU fins a un 118% de mitjana respecte al sistema base. A més, també redueix, al voltant d'un 57%, el consum energètic de la jerarquia de memòria. / [EN] In recent years, the growing need for computing capacity has become a challenge that has led the industry to look for alternative architectures to conventional out-of-order superscalar processors, with the goal of enabling an increase of computing power while achieving higher energy efficiency. GPU architectures, which just a decade ago were applied to accelerate computer graphics exclusively, have been one of the most employed alternatives for several years to reach the mentioned goal. A particular characteristic of GPUs is their high main memory bandwidth, which allows executing a large number of threads in a very efficient way. This feature, as well as their high computational power regarding floating-point operations, have caused the emergence of the GPGPU computing paradigm, where GPU architectures perform general purpose computations. The aforementioned characteristics make GPU devices very appropriate for the execution of massively parallel applications that have been traditionally executed in conventional high-performance processors. The work performed in this thesis aims to help improve the performance of GPUs in the execution of GPGPU applications. To this end, as a first step, a characterization study is carried out. In this study, the most important features of GPGPU applications, with respect to the memory hierarchy and its impact on performance, are identified. For this purpose, a detailed cycle-accurate simulator is used to model the architecture of a recent GPU. The study reveals that it is necessary to model with more detail some critical components of the GPU memory hierarchy in order to obtain accurate results. In addition, it shows that the achieved benefits can vary up to a factor of 3× depending on how these critical components are modeled. Due to this reason, as a second step before realizing a novel proposal, the work in this thesis focuses on determining which components of the GPU memory hierarchy must be modeled with more detail to increase the accuracy of simulator results and improving the existing simulator models of these components. Moreover, a validation study is performed comparing the results obtained with the improved GPU models against those from a real commercial GPU. The implemented simulator improvements reduce the deviation of the results obtained with the simulator from results obtained with the real GPU by about 96%. Finally, once simulation accuracy is increased, this thesis proposes a novel approach, called FRC (Fetch and Replacement Cache), which highly improves the GPU computational power by enhancing main memory-level parallelism. The proposal increases the number of parallel accesses to main memory by accelerating the management of fetch and replacement actions corresponding to those cache accesses that miss in the cache. The FRC approach is based on a small auxiliary cache structure that efficiently unclogs the memory subsystem, enhancing the GPU performance up to 118% on average compared to the studied baseline. In addition, the FRC approach reduces the energy consumption of the memory hierarchy by a 57%. / Candel Margaix, F. (2019). Efficient L2 Cache Management to Boost GPGPU Performance [Tesis doctoral]. Universitat Politècnica de València. https://doi.org/10.4995/Thesis/10251/125477 / Compendio