Esta tese tem por objetivo o desenvolvimento de metodologias eficientes e de baixo custo para ajustar as propriedades elétricas de OFETs de canal p e de canal n, a fim de possibilitar a fabricação do circuito complementar orgânico, semelhante a uma estrutura CMOS. O desempenho do circuito complementar fabricado foi otimizado, e também foi confeccionado por impressão um OFETs de canal operando em baixas tensões. Para a fabricação do CMOS orgânico foi proposto um método baseado na seleção adequada do solvente da camada dielétrica para ajustar o desempenho elétrico dos OFETs de canal p e de canal n. Os solventes, MEK, nBA e DMSO foram selecionados para a dissolução do PMMA por apresentarem diferenças nos valores de momento de dipolo, de ponto de ebulição e de graus de ortogonalidade em relação as camadas semicondutoras de P3HT e de P(NDI2OD-T2) dos OFETs. A análise dos resultados dos OFETs de canal p e de canal n demonstrou que a metodologia proposta é adequada tanto para o ajuste das propriedades elétricas destes dispositivos quanto para a otimização do desempenho dos mesmos. Os melhores desempenhos elétricos para os OFETs de canal p e de canal n foram obtidos quando utilizados o DMSO e o MEK como solventes do PMMA, respectivamente, devido à perfeita ortogonalidade destes solventes em relação às camadas semicondutoras. Os OFETs de canal p que utilizaram o DMSO e os OFETs de canal n que utilizaram o nBA foram os que apresentaram desempenhos elétricos semelhantes, sendo portanto aplicados na fabricação do CMOS. Valores de ganho entre 6,8 e 7,8 e de margem de ruído entre 28,3 V e 34,5 V foram obtidos para inversores complementares fabricados nesta etapa do trabalho. OFETs de canal p utilizando uma blenda de PTAA: diF TES ADT como camada semicondutora, o PEDOT:PSS como eletrodos dreno/fonte e o P(VDF-TrFE-CFE) como camada dielétrica também foram fabricados neste trabalho. A técnica de blade-coating foi utilizada para a deposição dos eletrodos dreno/fonte e da camada semicondutora, ao passo que a técnica de spray-coating foi utilizada para a deposição da camada dielétrica. Da análise dos resultados foi possível inferir que a utilização de um dielétrico com elevada constante dielétrica (K), como o P(VDF-TrFE-CFE), possibilita o funcionamento dos transistores a baixas tensões (≤ 8 V), porém com valores de mobilidade reduzidos devido à elevada desordem dipolar na interface provocada por este dielétrico. Para minimizar esses efeitos, uma fina camada de um polímero fluorado foi depositada entre a camada semicondutora e a dielétrica pela técnica de blade-coating, constituindo assim uma bicamada dielétrica nos OFETs. Dos resultados das medidas elétricas dos OFETs constituídos pela bicamada dielétrica foi observada permanência do funcionamento destes dispositivos a tensões inferiores a 8 V com desempenho elétricos superiores a resultados já publicados na literatura. Por fim, inversores lógicos unipolares com transistores de carga foram fabricados com os OFETs que utilizaram a bicamada dielétrica, sendo obtidos valores de ganho entre 1,2 e 1,6 e de margem de ruído entre 56% e 68,5% de ½ VDD. / This thesis aimed to develop an efficient and low cost method to adjust the electrical properties of p- and n-channel OFETs to allow us to build an organic CMOS and the optimization of printed p-channel OFETs to work at low voltages. We proposed a method to fabricate the organic CMOS, based on the careful selection of dielectric solvent, which was adjusted to obtain the best performance of p- and n-channel OFETs. The dielectric solvents as MEK, nBA and DMSO were selected to dissolve the PMMA dielectric polymer due their different physical properties as dipole moment and boiling point and because they showed slightly different degrees of orthogonality to the P3HT and P(NDI2OD-T2) semiconductor layers of the OFETs. The results showed that the careful selection of the dielectric solvent not only allows to tune the electrical characteristics of the p- and n-channel OFETs, but also to improve the performance of these devices. The best performances were achieved when DMSO and MEK were used as dielectric solvents of the p and n-channel OFETs, respectively, as result of the perfectly orthogonality of these solvents to the semiconductor layers. P-channel OFETs using DMSO and n-channel OFETs using nBA showed similar electrical characteristics and thus, they were used to construct the organic CMOS. The organic complementary inverters showed high gain and noise margin values in the range of 6,8 to 7,8 and 28,3 V to 34,5 V, respectively. Printed p-channel OFETs were also fabricated, in which the blend PTAA:diF TES ADT was used as semiconductor channel, PEDOT:PSS as the drain/source electrodes and P(VDF-TrFE-CFE) as the dielectric layer. The blade-coating technique was used to deposit the source/drain electrodes and the semiconductor layer, while the spray-coating technique was used to deposit the dielectric layer. It was observed that using high-k dielectric as P(VDF-TrFE-CFE) enable to reduce the operating voltage of the OFETs (≤8 V), however, this high-k dielectric also reduced the field effect mobility due the dipolar disorder at the semiconductor/dielectric interface. To minimize the dipolar issue at the interface, we inserted a thin fluoropolymer dielectric layer by blade-coating between the semiconductor and the high-k dielectric layers, thus constituting a dielectric bilayer on the OFETs. From the electrical measurements of the OFETs with the dielectric bilayer, it was observed that the devices were still working at 8 V and they also showed better performance in comparison to results already published. Finally, organic unipolar inverters with load transistors were fabricated using the p-channel OFETs with the dielectric bilayer and they showed reasonable performance, with gain and noise margin in the range of 1,2 to 1,6 and 56% e 68,5% of ½ VDD, respectively.

Os inversores multiníveis podem se beneficiar de filtros de saída reduzidos devido ao menor conteúdo harmônico do sinal sintetizado, dado que suas saídas possuem menores diferenças de tensão durante seu chaveamento. Sua desvantagem é causada pelo elevado número de chaves controladas normalmente necessário para seu funcionamento, e seus circuitos auxiliares. No objetivo de reduzir o número de chaves utilizadas em um inversor de sete níveis, uma nova topologia para um inversor de sete níveis de tensão é apresentada, construída a partir de duas fontes de tensão assimétricas conectadas em série e seis chaves semicondutoras. Este trabalho analisa os princípios de operação desta topologia e a lógica de chaveamento necessária para seu funcionamento. O arranjo proposto não oferece a possibilidade de redução de tensão sobre as chaves, conforme apresentado nas topologias clássicas de inversores com ponto neutro grampeado a diodo ou capacitor e de células em série, mas reduz a quantidade dos componentes necessários para a composição dos sete níveis, sendo possível utilizá-lo em inversores de baixa tensão, devido à seu menor tamanho e complexidade. O estudo apresenta a estrutura resultante em forma de um inversor monofásico por modulação de largura de pulso com disposição das portadoras em oposição de fase, com sete níveis igualmente espaçados, utilizando apenas seis chaves e duas fontes de tensão com alimentação assimétrica, em que a principal fonte tem o dobro da tensão da outra fonte. O funcionamento da topologia é verificado em simulação e implementação de protótipo de 860W. Uma outra versão também é apresentada analiticamente, com melhor grampeamento da tensão, utilizando oito chaves comandadas com uma lógica mais simplificada. Por fim, algumas propostas são sugeridas para a geração dos dois barramentos de tensão necessários. / Multilevel inverters can benefit from reduced output filters due to the lower harmonic content of the synthesized signal, since their outputs have lower voltage differences during their switching. Its disadvantage is caused by the high number of controlled switches and its auxiliary circuits normally required for its operation. In order to reduce the number of switches used in a seven-level inverter, a new topology for a seven level and its auxiliary circuits inverter is presented, constructed from two asymmetrical voltage sources connected in series and six semiconductor switches. This work analyzes the principles of operation of this topology and the switching logic required for its operation. The proposed arrangement does not offer the possibility of voltage reduction on the switches, as presented in the classical inverters topologies with diode or capacitor clamping or the series connected cells, but it reduces the amount of components necessary for the composition of the seven levels, being possible to use it in low voltages inverters, due to its smaller size and complexity. The study presents the resulting structure in the form of a single-phase inverter, using the pulse-width modulation with phase-contrast carriers technique, with seven equally spaced levels, using only six switches and two voltage sources with asymmetrical voltages, in which the main source has double the voltage of the other. The operation of the topology is checked with simulation and an implementation of a 860W prototype. Another version is also presented analytically, with better voltage clamping, using eight keys controlled with a more simplified logic. Finally, some proposals are suggested for the generation of the two necessary voltage rails.

Os sistemas fotovoltaicos tem se difundido mundialmente como uma tecnologia de energia limpa que pode ser utilizada na maior parte do planeta Terra. Isto o torna um sistema muito interessante para geração distribuída. A peça fundamental para o aproveitamento da energia fotovoltaica na geração distribuída é o inversor conectado a rede elétrica. Assim o rendimento deste equipamento influencia diretamente no aproveitamento da energia gerada pelos painéis fotovoltaicos e consequentemente no tempo em que o sistema se paga. O comportamento sazonal da geração de energia, onde o inversor trabalha na maior parte do tempo entre 10% e 90% da capacidade, principalmente em sistemas sem rastreamento, não permite que o inversor seja avaliado somente pelo seu rendimento em plena carga, mas pela curva de rendimento completa em toda faixa de operação. O método proposto para a melhora do rendimento do sistema em baixas potências é a utilização de inversores de baixa potência conectados a rede elétrica em paralelo trabalhando de maneira escalonada. Assim, em baixas potências o rendimento é mais elevado que se fosse utilizado um único inversor. Neste trabalho são avaliados também as consequências do paralelismo na taxa de distorção harmônica da corrente e as vantagens de ampliação na vida útil dos equipamentos e o recurso de redundância. Foram implementados 4 inversores de 300W de saída, na topologia ponte completa com frequência de comutação e amostragem de 21,6kHz, controlados cada um por um DSC 56F8014 da Freescale, e um dispositivo para monitoração dos inversores utilizando um microcontrolador PIC18F4520. Todos os dispositivos possuem interface de comunicação UART isolada com protocolo LIN. Os inversores foram testados em operação com modo de compartilhamento de potência contínuo, onde todos os inversores operam com parcelas identicas de potência, e no modo escalonado, onde os inversores entram em operação sob a demanda da potência a ser processada. Os resultados apresentam uma melhora de 3,7% no rendimento entre o sistema de compartilhamento de potência contínuo e escalonado, avaliados pelo rendimento ponderado do sistema (IEC-61836). / Photovoltaic systems have been spreading globally as a clean energy technology that can be used in most of the planet Earth. This makes it a very interesting system for distributed generation. The key to the use of photovoltaics in distributed generation inverter is connected to the power grid. Thus the performance of this equipment directly influences the use of energy generated by the photovoltaic panels and consequently the time that the system pays for itself. The seasonal behavior of power generation, where the drive works most of the time between 10% and 90% of capacity, especially in systems without tracking, does not allow the drive to be evaluated not only by their performance at full load, but the full yield curve throughout the operating range. The proposed method improves the system performance at low power is the use of low power inverters connected in parallel to mains electricity working in installments. Thus, in the low power output is higher than if a single drive were used. This work also evaluated the consequences of parallelism in the rate of harmonic current distortion and benefits of expanding the life of the equipment and the use of redundancy . We implemented four inverters 300W output full bridge topology with switching frequency of 21.6 kHz and sampling, each controlled by a Freescale 56F8014 DSC, and a device for monitoring the inverters using a PIC18F4520 microcontroler. All devices have isolated communication interface UART with LIN protocol. The inverters were tested in operation mode continuous power sharing , where all the inverters operate with identical plots power, and staggered where the inverters come into operation upon the demand of power being processed. The results show an improvement of 3,7% in revenue sharing system between the power and continued staggered valued at weighted yield of the system (IEC-61836). / 5000

Neste trabalho é proposto o desenvolvimento de um novo microinversor de estágio único para aplicação em sistemas fotovoltaicos. A topologia apresentada é baseada na combinação do conversor Cuk com uma estrutura de indutores chaveados para obtenção de um maior ganho estático e um circuito inversor em ponte completa conectado à rede. A estrutura de indutores chaveados apresentada nesse trabalho reduz esforços de tensão e corrente nas chaves semicondutoras. Com o objetivo de facilitar o controle, a etapa CC do microinversor opera em modo de condução descontínua (DCM). Para injetar corrente senoidal com baixa distorção harmônica à rede, é aplicado às chaves semicondutoras da etapa CC uma modulação por largura de pulso senoidal (SPWM). As chaves semicondutoras do circuito inversor em ponte completa são comandadas na frequência da rede, reduzindo perdas por chaveamento. Por se tratar de uma topologia inédita, são apresentados os modos de operação e a análise matemática do conversor CC-CC Cuk com alto ganho estático. Posteriormente, são realizadas a análise teórica e a estratégia de controle do microinversor proposto. Os resultados experimentais são expostos para discutir o funcionamento da topologia proposta, através de simulações e da implementação de um protótipo de 180 W. / The development of a novel single stage microinverter is proposed. The presented topology is based on the combination of the Cuk converter with a switched inductor structure to obtain a higher static gain, and a full-bridge inverter circuit. The presented switched inductor structure reduces voltage and current stresses on the power switches. In order of simplify the control, the stage CC of the microinverter operate in discontinuous conduction mode (DCM). To inject sinusoidal current with low harmonic distortion to the grid, a sinusoidal pulse width modulation (SPWM) is applied in the power switches. The switches of the full-bridge invertes are commanded in low frequency, in order to reduce switching losses. Operation modes and math analysis of the novel CC-CC converter are presented. Moreover, the math analysis and control strategy of proposed microinverter topology are exposed. Furthermore, experimental results are performed to analyze the proposed topology operation, by software simulations and implementation of a 180 W prototype.

Os sistemas fotovoltaicos tem se difundido mundialmente como uma tecnologia de energia limpa que pode ser utilizada na maior parte do planeta Terra. Isto o torna um sistema muito interessante para geração distribuída. A peça fundamental para o aproveitamento da energia fotovoltaica na geração distribuída é o inversor conectado a rede elétrica. Assim o rendimento deste equipamento influencia diretamente no aproveitamento da energia gerada pelos painéis fotovoltaicos e consequentemente no tempo em que o sistema se paga. O comportamento sazonal da geração de energia, onde o inversor trabalha na maior parte do tempo entre 10% e 90% da capacidade, principalmente em sistemas sem rastreamento, não permite que o inversor seja avaliado somente pelo seu rendimento em plena carga, mas pela curva de rendimento completa em toda faixa de operação. O método proposto para a melhora do rendimento do sistema em baixas potências é a utilização de inversores de baixa potência conectados a rede elétrica em paralelo trabalhando de maneira escalonada. Assim, em baixas potências o rendimento é mais elevado que se fosse utilizado um único inversor. Neste trabalho são avaliados também as consequências do paralelismo na taxa de distorção harmônica da corrente e as vantagens de ampliação na vida útil dos equipamentos e o recurso de redundância. Foram implementados 4 inversores de 300W de saída, na topologia ponte completa com frequência de comutação e amostragem de 21,6kHz, controlados cada um por um DSC 56F8014 da Freescale, e um dispositivo para monitoração dos inversores utilizando um microcontrolador PIC18F4520. Todos os dispositivos possuem interface de comunicação UART isolada com protocolo LIN. Os inversores foram testados em operação com modo de compartilhamento de potência contínuo, onde todos os inversores operam com parcelas identicas de potência, e no modo escalonado, onde os inversores entram em operação sob a demanda da potência a ser processada. Os resultados apresentam uma melhora de 3,7% no rendimento entre o sistema de compartilhamento de potência contínuo e escalonado, avaliados pelo rendimento ponderado do sistema (IEC-61836). / Photovoltaic systems have been spreading globally as a clean energy technology that can be used in most of the planet Earth. This makes it a very interesting system for distributed generation. The key to the use of photovoltaics in distributed generation inverter is connected to the power grid. Thus the performance of this equipment directly influences the use of energy generated by the photovoltaic panels and consequently the time that the system pays for itself. The seasonal behavior of power generation, where the drive works most of the time between 10% and 90% of capacity, especially in systems without tracking, does not allow the drive to be evaluated not only by their performance at full load, but the full yield curve throughout the operating range. The proposed method improves the system performance at low power is the use of low power inverters connected in parallel to mains electricity working in installments. Thus, in the low power output is higher than if a single drive were used. This work also evaluated the consequences of parallelism in the rate of harmonic current distortion and benefits of expanding the life of the equipment and the use of redundancy . We implemented four inverters 300W output full bridge topology with switching frequency of 21.6 kHz and sampling, each controlled by a Freescale 56F8014 DSC, and a device for monitoring the inverters using a PIC18F4520 microcontroler. All devices have isolated communication interface UART with LIN protocol. The inverters were tested in operation mode continuous power sharing , where all the inverters operate with identical plots power, and staggered where the inverters come into operation upon the demand of power being processed. The results show an improvement of 3,7% in revenue sharing system between the power and continued staggered valued at weighted yield of the system (IEC-61836). / 5000

Neste trabalho é proposto o desenvolvimento de um novo microinversor de estágio único para aplicação em sistemas fotovoltaicos. A topologia apresentada é baseada na combinação do conversor Cuk com uma estrutura de indutores chaveados para obtenção de um maior ganho estático e um circuito inversor em ponte completa conectado à rede. A estrutura de indutores chaveados apresentada nesse trabalho reduz esforços de tensão e corrente nas chaves semicondutoras. Com o objetivo de facilitar o controle, a etapa CC do microinversor opera em modo de condução descontínua (DCM). Para injetar corrente senoidal com baixa distorção harmônica à rede, é aplicado às chaves semicondutoras da etapa CC uma modulação por largura de pulso senoidal (SPWM). As chaves semicondutoras do circuito inversor em ponte completa são comandadas na frequência da rede, reduzindo perdas por chaveamento. Por se tratar de uma topologia inédita, são apresentados os modos de operação e a análise matemática do conversor CC-CC Cuk com alto ganho estático. Posteriormente, são realizadas a análise teórica e a estratégia de controle do microinversor proposto. Os resultados experimentais são expostos para discutir o funcionamento da topologia proposta, através de simulações e da implementação de um protótipo de 180 W. / The development of a novel single stage microinverter is proposed. The presented topology is based on the combination of the Cuk converter with a switched inductor structure to obtain a higher static gain, and a full-bridge inverter circuit. The presented switched inductor structure reduces voltage and current stresses on the power switches. In order of simplify the control, the stage CC of the microinverter operate in discontinuous conduction mode (DCM). To inject sinusoidal current with low harmonic distortion to the grid, a sinusoidal pulse width modulation (SPWM) is applied in the power switches. The switches of the full-bridge invertes are commanded in low frequency, in order to reduce switching losses. Operation modes and math analysis of the novel CC-CC converter are presented. Moreover, the math analysis and control strategy of proposed microinverter topology are exposed. Furthermore, experimental results are performed to analyze the proposed topology operation, by software simulations and implementation of a 180 W prototype.

Made available in DSpace on 2016-08-17T16:54:34Z (GMT). No. of bitstreams: 1 Tese Jose Gomes de Matos.pdf: 8310310 bytes, checksum: b4d88d65be5edbb4f214f9dd09ed8f3b (MD5) Previous issue date: 2014-03-31 / Conselho Nacional de Desenvolvimento Científico e Tecnológico / This work proposes a new strategy to control the generated power in an alternating current autonomous microgrid that has distributed generators and battery banks. There are no restrictions regarding the type of generator to be connected, however in this particular study the effectiveness of the proposed strategy is analyzed by considering that the power source is a wind turbine coupled to a permanent magnet synchronous generator. The microgrid analyzed consists of at least one bidirectional electronic converter powered by a battery bank, which has the function of forming the microgrid; an electronic converter connected to a wind turbine generator, which operates as a power supplier to the microgrid; loads, and other peripheral systems of control and maneuver. The main objective of the proposed strategy is to maintain the terminal voltages of battery banks under control and below its upper limit, even when momentarily the power demanded by the loads connected to the microgrid is less than the power sources generation capacity. The proposed strategy controls the terminal voltage of the battery banks, controlling the power output that comes from the generators. This is done without the use of dump loads or any physical communication between the electronic converters connected to the battery banks and the electronic converters connected to the generators. A modified droop control technique, based on the grid frequency, is used to inform to the power generator electronic converters on the amount of energy they need to generate in order to maintain the state of charge of the battery banks below their limits. The work also presents the methodology to design and tuning the controllers of the associated variables of the generation system. This includes the voltage and frequency grid, the active and reactive power generated by the generators, the DC bus voltages in all electronic power converters and the terminal voltage of the battery banks. All controllers are designed in the discrete domain. A strategy to decouple the effects of the input disturbances is incorporated, into each controller. Special attention is given to the grid voltage controller due the fact that the effect of the load current disturbance is very significant for the grid power quality. Issues x related to the operation of the wind turbine on its maximum power point are also addressed in the control of the power electronic converter connected to the generator. The control strategy proposed in this study is validated through experimental results obtained using a microgrid prototype of 15 kW rated power. / Este trabalho propõe uma nova estratégia para controle da potência gerada em uma microrrede isolada, que opera em corrente alternada e que dispõe de geradores e bancos de baterias distribuídos ao longo da mesma. Embora não haja restrições quanto ao tipo de gerador a ser conectado à microrrede, neste estudo a aplicabilidade da estratégia proposta é analisada considerando a fonte de potência como sendo uma turbina eólica acoplada a um gerador síncrono a imãs permanentes. A microrrede estudada é composta de um conversor eletrônico bidirecional, alimentado por um banco de baterias, que tem a função de formar a microrrede; um conversor eletrônico ligado ao gerador da turbina eólica e que funciona como alimentador da microrrede; além das cargas e demais sistemas periféricos de controle e manobra. O principal objetivo dessa estratégia é controlar a tensão terminal dos bancos de baterias abaixo de um determinado valor limite, mesmo quando momentaneamente a potência demandada pela carga conectada à microrrede seja inferior à capacidade de geração das fontes de potência. A estratégia proposta controla a tensão dos bancos de baterias, controlando a energia gerada que vem dos geradores. Isto é feito sem a utilização de carga auxiliar para consumir o excesso de energia e sem comunicação física entre os conversores eletrônicos dos bancos de baterias e os conversores eletrônicos conectados aos geradores. Uma técnica de controle droop modificada, com base na frequência da microrrede, é usada para informar aos conversores dos geradores sobre a quantidade de energia que eles estão liberados para gerar, a fim de manter a tensão dos bancos de baterias abaixo dos seus valores limites. O trabalho ainda apresenta as sistemáticas de projeto e sintonia dos controladores das variáveis associadas com o sistema de geração. Isso compreende o controle da tensão e da frequência da microrrede, o controle das tensões nos barramentos de corrente contínua de todos os conversores eletrônicos de potência e o controle da tensão terminal dos bancos de baterias. Todos os controladores são projetados no domínio discreto. Uma estratégia de desacoplamento dos efeitos das entradas de perturbações é incorporada a cada controlador. Nesse enfoque, é dada atenção especial ao controlador de tensão da microrrede, cujo efeito da viii perturbação da corrente da carga é muito significativo para a qualidade de energia do sistema de geração. As questões relativas à maximização do aproveitamento energético das fontes renováveis são contempladas no controle do conversor da turbina eólica. A estratégia de controle proposta neste trabalho é validada a partir de resultados experimentais obtidos com um protótipo de microrrede de potência nominal 15 kw.

La prolifération des composants électroniques fait que l'étude de leur vulnérabilité face à des agressions électromagnétiques intentionnelles ou non devient de plus en plus préoccupante. Notre étude s'inscrit dans ce contexte et s'oriente plus particulièrement vers les composants numériques. Ces derniers incorporent généralement, à toutes leurs interfaces d'entrée et de sortie, des éléments de protection contre les décharges électrostatiques permettant d'éliminer tout signal se présentant avec une amplitude élevée. Cependant, les signaux perturbateurs peuvent avoir des amplitudes moindres mais des formes d'onde complexes et capables de causer des dysfonctionnements à ces composants numériques sans activer les protections. Dans ce cas, les étages d'entrée se retrouvent au premier plan et leur comportement face à ces signaux perturbateurs peut altérer la fonctionnalité globale du circuit. Ainsi, nous nous sommes proposés d'étudier et de modéliser les comportements de ces étages d'entrée face à ces types d'agressions. Une première étape a consisté à définir une plateforme d'expérimentation pour les composants numériques. Une sélection des types de composants de test a d'abord été effectuée et le choix s'est porté naturellement sur l'inverseur CMOS, car il est présent sur la quasi-totalité des étages d'entrée, et sa structure est simple et connue. Le choix de cette technologie est également dicté par sa simplicité et son omniprésence dans les équipements électroniques actuels. Différents types de signaux perturbateurs ont été appliqués à ces inverseurs CMOS afin d'observer et de relever leurs comportements typiques et particuliers. Ensuite, à partir des résultats expérimentaux, un modèle SPICE comportemental et générique des inverseurs CMOS a été créé. Différents types de modèles de composants numériques existent mais le type SPICE est le seul à expliciter leur architecture complète. En effet, pour des raisons liées aux propriétés intellectuelles, les fabricants sont généralement discrets sur les structures internes de leurs circuits intégrés. Par contre, ces modèles SPICE ne sont à priori valables que dans des limites de fonctionnement définis par les fabricants. Nous avons apporté diverses modifications à ce modèle afin d'incorporer les comportements observés en dehors des limites de fonctionnement des inverseurs CMOS. Le besoin de trouver un modèle générique a imposé d'étudier un grand nombre d'échantillons d'inverseurs CMOS de différents fabricants et de différentes familles technologies. Enfin, une synthèse des résultats de simulations et des modèles, en fonction des fabricants et des familles technologiques, a été réalisée sous forme d'un tableau récapitulatif. / The proliferation of electronic components increases the interest of investigations about their vulnerability against electromagnetic interference intentionally emitted or not. Our study falls in this context and is specifically devoted to digital devices. These devices usually include, at their input/output ports, protection elements to prevent against electrostatic discharges and all kind of signals with very high amplitude. However, the perturbating signals can have low amplitude and complex waveforms that can cause trouble to these digital devices without triggering protection elements. In this case, first stages are the front, and their behaviors against these perturbation signals can alter the good operation of the device. Thus, we propose to study and model the behaviors of these first stages against such aggressions. First of all, an experimental platform was defined for the digital devices. A selection of devices is done and CMOS inverter was naturally chosen because of its presence in almost all of the first stages of digital devices, and because its structure is simple and well known. The choice of the CMOS technology is also due to its simplicity and omnipresence in current electronic equipments. Different perturbation signals were applied to these CMOS inverters to observe and record their typical and particular behaviors. Secondly, with the experimental results, a behavioral and generic SPICE model of CMOS inverters was developed. Different models exist for digital devices, but SPICE is the only one explicitly describing their complete architecture. But, for intellectual proprieties reasons, the manufacturers are usually reluctant to share information on their devices’ internals. However, the SPICE models are only valid within some operating limits defined by manufacturers. We have brought different modifications to this SPICE model to incorporate the observed behaviors of CMOS inverters inside and outside their normal operating conditions. The generic criterion of the final model imposed to study a large number of CMOS inverters of different manufacturers and different logic families. Finally, a synthesis of models and simulation results, by manufacturer and logic family, is produced.

The inverter dead-time is integral to the safety of a voltage source inverter (VSI). Dead-time is introduced between the complementary gating signals of the top and bottom switches in each VSI leg to prevent shoot-through fault. This thesis reports and investigates dead-time induced sub-harmonic oscillations in open-loop induction motor drives of different power levels, under light-load conditions. The thesis develops mathematical models that help understand and predict the oscillatory behaviour of such motor drives due to dead-time act. Models are also developed to study the impact of under-compensation and over-compensation of dead-time act on stability. The various models are validated through extensive simulations and experimental results. The thesis also proposes and validates active damping schemes for mitigation of such sub-harmonic oscillations. The thesis reports high-amplitude sub-harmonic oscillations in the stator current, torque and speed of a 100-kW open-loop induction motor drive in the laboratory, operating under no-load. Experimental studies, carried out on 22-kW, 11-kW, 7.5-kW and 3.7-kW open-loop induction motor drives, establish the prevalence of dead-time induced sub-harmonic oscillations in open-loop motor drives of different power levels. An experimental procedure is established for systematic study of this phenomenon in industrial drives. This procedure yields the operating region, if any, where the motor drive is oscillatory. As a first step towards understanding the oscillatory behaviour of the motor drive, a mathematical model of the VSI is derived in a synchronously revolving reference frame (SRF), incorporating the of dead-time on the inverter output voltage. This leads to a modified dynamic model of the inverter-fed induction motor in the SRF, inclusive of the dead-time act. While the rotor dynamic equations are already non-linear, dead-time is found to introduce nonlinearities in the stator dynamic equations as well. The nonlinearities in the modified dynamic model make even the steady solution non-trivial. Under steady conditions, the dead-time can be modelled as the drop across an equivalent resistance (Req0) in the stator circuit. A precise method to evaluate the equivalent resistance Req0 and a simple method to arrive at the steady solution are proposed and validated. For the purpose of stability analysis, a small-signal model of the drive is then derived by linearizing the non-linear dynamic equations of the motor drive, about a steady-state operating point. The proposed small-signal model shows that dead-time contributes to different values of equivalent resistances along the q-axis and d-axis and also to equivalent cross-coupling reactance’s that appear in series with the stator windings. Stability analysis performed using the proposed model brings out the region of oscillatory behaviour (or region of small-signal instability) of the 100-kW motor drive on the voltage versus frequency (V- f) plane, considering no-load. The oscillatory region predicted by the small-signal analysis is in good agreement with simulations and practical observations for the 100-kW motor drive. The small-signal analysis is also able to predict the region of oscillatory behaviour of an 11-kW motor drive, which is con consumed by simulations and experiments. The analysis also predicts the frequencies of sub-harmonic oscillations at different operating points quite well for both the drives. Having the validity of the small-signal analysis at different power levels, this analytical procedure is used to predict the regions of oscillatory behaviour of 2-pole, 4-pole, 6-pole and 8-pole induction motors rated 55 kW and 110 kW. The impact of dead-time on inverter output voltage has been studied widely in literature. This thesis studies the influence of dead-time on the inverter input current as well. Based on this study, the dynamic model of the inverter fed induction motor is extended to include the dc-link dynamics as well. Simulation results based on this extended model tally well with the experimentally measured dc-link voltage and stator current waveforms in the 100-kW drive. Dead-time compensation may be employed to mitigate the dead-time and oscillatory behaviour of the drive. However, accurate dead-time compensation is challenging to achieve due to various factors such as delays in gate drivers, device switching characteristics, etc. Effects of under-compensation and over-compensation of dead time are investigated in this thesis. Under-compensation is shown to result in the same kind of oscillatory behaviour as observed with dead-time, but the fundamental frequency range over which such oscillations occur is reduced. On the other hand, over-compensation of dead-time effect is shown to result in a different kind of oscillatory behaviour. These two types of oscillatory behaviour due to under- and over-compensation, respectively, are distinguished and demonstrated by analyses, simulations and experiments on the 100-kW drive. To mitigate the oscillatory behaviour of the drive, an active damping scheme is proposed. This scheme emulates the effect of an external inductor in series with the stator winding. A small-signal model is proposed for an induction motor drive with the proposed active damping scheme. Simulations and experiments on the 100-kW drive demonstrate effective mitigation of light-load instability with this active damping scheme. In the above inductance emulation scheme, the emulated inductance is seen by the sub-harmonic components, fundamental component as well as low-order harmonic components of the motor current. Since the emulated inductance is also seen by the fundamental component, there is a fundamental voltage drop across the emulated inductance, leading to reduced co-operation of the induction motor. Hence, an improved active damping scheme is proposed wherein the emulated inductance is seen only by the sub-harmonic and low-order harmonic components. This is achieved through appropriate altering in the synchronously revolving domain. The proposed improved active damping scheme is shown to mitigate the sub-harmonic oscillation effectively without any reduction in flux.

Renewable energy sources normally require power converters to convert their energy into standardized regulated ac output. The motivation for this thesis is to design and control power converters for renewable energy systems to ensure very good power quality, efficiency and reliability. The renewable energy sources considered are low voltage dc sources such as photovoltaic (PV) modules. Two transformer-isolated power circuit topologies with input voltage of less than 50V are designed and developed for low and medium power applications. Various design and control issues of these converters are identified and new solutions are proposed. For low power rating of a few hundred watts, a line-frequency transformer interfaced inverter is developed. In the grid connected operation, it is observed that this topology injects considerable lower order odd and even harmonics in the grid current. The reasons for this are identified. A new current control method using adaptive harmonic compensation technique and a proportional-resonant-integral (PRI) controller is proposed. The proposed current controller is designed to ensure that the grid current harmonics are within the limits set by the IEEE 1547-2003 standard. Phase-locked loops (PLLs) are used for grid synchronization of power converters in grid-tied operation and for closed-loop control reference generation. Analysis and design of synchronous reference frame PLL (SRF-PLL) and second-order generalized integrator (SOGI) based PLLs considering unit vector distortion under the possible non-ideal grid conditions of harmonics, unbalance, dc offsets and frequency deviations are proposed and validated. Both SRF-PLL and SOGI-PLL are low-complexity PLLs. The proposed designs achieve fastest settling time for these PLLs for a given worst-case input condition. The harmonic distortion and dc offsets in the resulting unit vectors are limited to be well within the limits set by the IEEE 1547-2003 standard. The proposed designs can be used to achieve very good performance using conventional low-complexity PLLs without the requirement of advanced PLLs which can be computationally intensive. A high-frequency (HF) transformer interfaced ac link inverter with a lossless snubber is developed medium power level in the order of few kilowatts. The HF transformer makes the topology compact and economical compared to an equally rated line frequency transformer. A new synchronized modulation method is proposed to suppress the possible over-voltages due to current commutation in the leakage inductance of the HF transformer. The effect of circuit non-ideality of turn-on delay time is analyzed. The proposed modulation mitigates the problem of spurious turn-on that can occur due to the turn-on delay time. The HF inverter, rectifier and snubber devices have soft switching with this modulation. A new reliable start-up method is proposed for this inverter topology without any additional start- up circuitry. This solves the problems of over-voltages and inrush currents during start-up. The overall research work reported in the thesis shows that it is possible to have compact, reliable and high performance power converters for renewable energy conversion systems. It is also shown that high control performance and power quality can be achieved using the proposed control techniques of low implementation complexity.