Spelling suggestions: "subject:"[een] MULTIPROCESSOR"" "subject:"[enn] MULTIPROCESSOR""
1 |
Performance Evaluation of A Multiprocessor Support for Concurrent Execution of Critical SectionsChang, Heng-Hao 01 October 2001 (has links)
In this research, in order to improve the concurrency of critical sections on distributed shared memory multiprocessors, we designed various concurrency control support for critical sections and simulate its system performance simulation. The system features consist of:
|
2 |
General theory relating to the implementation of concurrent symbolic computationClarke, Thomas James Woodchurch January 1989 (has links)
No description available.
|
3 |
Emulation of a virtual shared memory architectureRaina, Sanjay January 1993 (has links)
No description available.
|
4 |
A multiprocessor system for real-time image generationSerra del Molino, L. January 1987 (has links)
No description available.
|
5 |
A demand driven multiprocessorBakti, Zulkifli Abdul Kadir January 1985 (has links)
It is thought that fast low cost computers can be built by employing large numbers of cheap microprocessors working together in a system. However increasing the number of microprocessors in a parallel computer system may not produce a linear increase in performance for general purpose programming. The problems seem to lie in the communication between processors and the method of exploiting parallelism. A multiprocessor system was constructed using six MC68000 microprocessors. The problems of communication and exploiting parallelism were tackled in the design of the multiprocessor system. The component processors in a multiprocessor system communicate with each other through a communication channel. It is essential that the communication hardware has a high bandwidth. A fast communication hardware was implemented based on a two port shared memory. One method of extracting parallelism in a computing problem is by using divide and conquer. A software system was developed that enables the multiprocessor to exploit parallelism derived by the divide and conquer method. A software kernel is employed to manage the scheduling of parallel tasks to processors and the communication between processors. The mode of computation is based on the demand driven model.
|
6 |
Benchmarks for Embedded Multi-processorsGong, Shaojie, Deng, Zhongping January 2007 (has links)
<p>During the recent years, computer performance has increased dramatically. To measure </p><p>the performance of computers, benchmarks are ideal tools. Benchmarks exist in many </p><p>areas and point to different applications. For instance, in a normal PC, benchmarks can be </p><p>used to test the performance of the whole system which includes the CPU, graphic card, </p><p>memory system, etc. For multiprocessor systems, there also exist open source benchmark </p><p>programs. In our project, we gathered information about some open benchmark programs </p><p>and investigated their applicability for evaluating embedded multiprocessor systems </p><p>intended for radar signal processing. During our investigation, parallel cluster systems </p><p>and embedded multiprocessor systems were studied. Two benchmark programs, HPL and </p><p>NAS Parallel Benchmark were identified as particularly relevant for the application field. </p><p>The benchmark testing was done on a parallel cluster system which has an architecture </p><p>that is similar to the architecture of embedded multiprocessor systems, used for radar </p><p>signal processing.</p>
|
7 |
Benchmarks for Embedded Multi-processorsGong, Shaojie, Deng, Zhongping January 2007 (has links)
During the recent years, computer performance has increased dramatically. To measure the performance of computers, benchmarks are ideal tools. Benchmarks exist in many areas and point to different applications. For instance, in a normal PC, benchmarks can be used to test the performance of the whole system which includes the CPU, graphic card, memory system, etc. For multiprocessor systems, there also exist open source benchmark programs. In our project, we gathered information about some open benchmark programs and investigated their applicability for evaluating embedded multiprocessor systems intended for radar signal processing. During our investigation, parallel cluster systems and embedded multiprocessor systems were studied. Two benchmark programs, HPL and NAS Parallel Benchmark were identified as particularly relevant for the application field. The benchmark testing was done on a parallel cluster system which has an architecture that is similar to the architecture of embedded multiprocessor systems, used for radar signal processing.
|
8 |
Communication mapping in multiprocessor platformsCoêlho de Araújo, Cristiano January 2005 (has links)
Made available in DSpace on 2014-06-12T15:54:34Z (GMT). No. of bitstreams: 2
arquivo7168_1.pdf: 2138979 bytes, checksum: 19e8ea84018aa698112c01c9de47d857 (MD5)
license.txt: 1748 bytes, checksum: 8a4605be74aa9ea9d79846c1fba20a33 (MD5)
Previous issue date: 2005 / Os avanços na tecnologia de fabricação de circuitos integrados tem permitido a implementação de sistemas inteiros em um único chip, combinando alto poder de processamento e baixo consumo em uma pequena área. Os chamados Multiprocessor System-on-Chip (MPSoc) incluem multiplos processadores heterogeneos, estruturas complexas de interconexão e componentes de propriedade intelectual fornecidos por terceiros. Esta tecnologia permitiu o surgimento de dispositivos portateis como telefones celulares, PDAs, dispositivos multimídia que combinam a portabilidade com a capacidade de antigos computadores desktop. Contudo, a especificação e validação destes sistemas se tornou uma tarefa muito difícil. Existe um gap entre a especificação do sistema em alto nível e a implementação em uma plataforma multirprocessador. Este gap entre a especificação e a implementação não é tratado de forma adequada pelas metodologias e ferramentas existentes. Tendo como consequencia atrasos no ciclo de desenvolvimento e erros que podem comprometer o projeto. Nesta tese é atacado o problema de implementação da comunicação modelada a nível de sistema em plataformas multiprocessadores. As contribuições deste trabalho são: (1) uma nova abordagem para a modelagem de plataformas multiprocessador; (2) uma metodologia para o mapeamento de comunicação na plataforma; (3) suporte de análise para avaliação da implementação da comunicação. As metodologias e ferramentas propostas foram validadas utilizando-se dois estudos de caso. O primeiro uma aplicação com múltiplas comunicações e o segundo uma aplicação multimídia
|
9 |
A flexible, scalable approach to real-time graphicsShrubsole, Paul Anthony January 2000 (has links)
No description available.
|
10 |
ACCELERATING REAL-TIME SPACE DATA PACKET PROCESSINGDowling, Jason, Welling, John, Aerosys, Loral, Nanzetta, Kathy, Bennett, Toby, Shi, Jeff 11 1900 (has links)
International Telemetering Conference Proceedings / October 30-November 02, 1995 / Riviera Hotel, Las Vegas, Nevada / NASA’s use of high bandwidth packetized Consultative Committee for Space Data
Systems (CCSDS) telemetry in future missions presents a great challenge to ground
data system developers. These missions, including the Earth Observing System
(EOS), call for high data rate interfaces and small packet sizes. Because each packet
requires a similar amount of protocol processing, high data rates and small packet
sizes dramatically increase the real-time workload on ground packet processing
systems.
NASA’s Goddard Space Flight Center has been developing packet processing
subsystems for more than twelve years. Implementations of these subsystems have
ranged from mini-computers to single-card VLSI multiprocessor subsystems. The
latter subsystem, known as the VLSI Packet Processor, was first deployed in 1991 for
use in support of the Solar Anomalous & Magnetospheric Particle Explorer
(SAMPEX) mission. An upgraded version of this VMEBus card, first deployed for
Space Station flight hardware verification, has demonstrated sustained throughput of
up to 50 Megabits per second and 15,000 packets per second. Future space missions
including EOS will require significantly higher data and packet rate performance. A
new approach to packet processing is under development that will not only increase
performance levels by at least a factor of six but also reduce subsystem replication
costs by a factor of five. This paper will discuss the development of a next generation
packet processing subsystem and the architectural changes necessary to achieve a
thirty-fold improvement in the performance/price of real-time packet processing.
|
Page generated in 0.0363 seconds